Access-in-turn test architecture for low-power test application

Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill

(2016) Dong Xiang et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption

(2015) Urban Ingelsson et al.   IEEE TRANSACTIONS ON COMPUTERS

Harzard-Based ATPG for Improving Delay Test Quality

(2015) Tieqiao Liu et al.   JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS

Scan power-aware deterministic test scheme using a low-transition linear decompressor

(2014) Weizheng Wang et al.   INTERNATIONAL JOURNAL OF ELECTRONICS

Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing

(2013) Samah Mohamed Saeed et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating

(2013) Shmuel Wimer et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

On X-Variable Filling and Flipping for Capture-Power Reduction in Linear Decompressor-Based Test Compression Environment

(2012) Xiao Liu et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies

(2011) Chunhua Yao et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Low-Power Scan Operation in Test Compression Environment

(2009) D. Czysz et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture

(2009) Dong Xiang et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Low-Power Test Data Application in EDT Environment Through Decompressor Freeze

(2008) Dariusz Czysz et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS