Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 69, Issue 2, Pages 530-540Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2021.3121418
Keywords
Transfer functions; Quantization (signal); Pipelines; Bandwidth; Delays; Switches; Delay lines; Pipeline; delay; quantizer; residue; frequency scaling; residue; quantization noise
Categories
Funding
- RF, Analog and Mixed Signal Laboratory, IIT Madras
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Continuous-time pipelined (CTP) ADC is a promising high-speed analog-to-digital conversion technique that achieves anti-alias filtering and analog-to-digital conversion in one step. However, the performance of such converters is degraded by RC time-constant shifts caused by changes in ambient temperature.
The continuous-time pipelined (CTP) ADC is a promising emerging high-speed analog-to-digital conversion technique that achieves anti-alias filtering and analog-to-digital conversion in one step. Driving such a converter is easy, thanks to its resistive input impedance. RC time-constant shifts, which will occur in practice due to a change in ambient temperature, degrade the performance of such converters. The aim of this work is to understand this phenomenon, quantify the resulting SNDR degradation, and thereby derive design tradeoffs. The theory is compared with measurements from a three-stage CTP that targets 70,dB SNDR in a 100,MHz bandwidth while sampling at 800,MS/s.
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