A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS

This work presents a single-channel, fully dynamic pipelined-SAR ADC with relaxed architectural tradeoffs thanks to the use of ring amplification and background calibration. It leverages a novel SAR quantizer and narrowband dither injection to achieve fast and comprehensive background calibration of DAC mismatch, interstage gain, and ring amplifier (ringamp) linearity and bias optimality. The ADC also includes an on-chip, wide-range, fully dynamic reference regulation system. Implemented in 16-nm CMOS, it consumes 3.3 mW at 500 MS/s (including regulation) and achieves 10.1 ENOB and 75.5-dB SFDR, resulting in Schreier and Walden figure-of-merit (FoM) values of 171.1 dB and 6.2 fJ/conv.-step, respectively.

Automated summary

This work presents a single-channel, fully dynamic pipelined-SAR ADC that utilizes ring amplification and background calibration for relaxed architectural tradeoffs. It achieves fast and comprehensive calibration of DAC mismatch, interstage gain, and ring amplifier linearity and bias optimality through a novel SAR quantizer and narrowband dither injection. The ADC also includes an on-chip, wide-range, fully dynamic reference regulation system. Implemented in 16-nm CMOS, it consumes 3.3 mW at 500 MS/s (including regulation) and achieves 10.1 ENOB and 75.5-dB SFDR, resulting in Schreier and Walden figure-of-merit values of 171.1 dB and 6.2 fJ/conv.-step, respectively.