Article
Computer Science, Theory & Methods
Emanuele Del Sozzo, Davide Conficconi, Alberto Zeni, Mirko Salaris, Donatella Sciuto, Marco D. Santambrogio
Summary: This article surveys three leading digital design abstractions for FPGAs: HDLs, HLS tools, and DSLs, and provides a taxonomy and timeline for each abstraction trend.
ACM COMPUTING SURVEYS
(2023)
Article
Computer Science, Hardware & Architecture
Yi-Fan Zhang, Lei Sun, Qiang Cao
Summary: This paper proposes a three-level parallel architecture, TLP-LDPC, to achieve high throughput LDPC decoding on large FPGA platforms. By fully exploiting the characteristics of LDPC and underlying hardware, and eliminating potential data conflicts, this decoder provides high decoding performance.
JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
(2022)
Article
Computer Science, Artificial Intelligence
Alexandro Ortiz, Efrain Mendez, David Balderas, Pedro Ponce, Israel Macias, Arturo Molina
Summary: This study describes the implementation of metaheuristic optimization algorithms in hardware and compares five important algorithms. The results demonstrate the feasibility of NI FPGA hardware and reveal differences in device utilization and execution time among the algorithms.
APPLIED SOFT COMPUTING
(2021)
Article
Computer Science, Hardware & Architecture
Young-Kyu Choi, Yuze Chi, Jason Lau, Jason Cong
Summary: Streaming applications can be optimized through free-running optimization, which simplifies the control logic without impacting clock frequency or performance. However, determining when to apply this optimization without changing the original functionality is challenging, and manually applying it to legacy codes is time-consuming. This article presents the TARO framework, which automatically applies free-running optimization to HLS-based streaming applications. Experimental results on Alveo U250 demonstrate an average reduction of 16% LUT and 45% FF for streaming-based systolic array designs.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2023)
Article
Engineering, Electrical & Electronic
Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
Summary: Digital down converters (DDCs) are widely used in modern communication systems, such as software-defined radios (SDRs), to convert digitized, band-limited signals to lower frequency signals for simplifying subsequent filtering stages. This study presents a low-power- and area-optimized implementation of a DDC for SDR applications, achieved through innovative high-level synthesis (HLS) design methods based on application-specific bit widths for data nodes. The results show superior area and power efficiency compared to hand-coded RTL implementations, with almost the same operational speed.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
(2021)
Article
Geochemistry & Geophysics
Daniel Bascones, Carlos Gonzalez, Daniel Mozos
Summary: This article presents a real-time implementation of a hyperspectral image compression algorithm based on FPGA, which is able to process large images at a fast speed. The algorithm avoids new dependencies by using a new sample ordering method and encoder.
IEEE TRANSACTIONS ON GEOSCIENCE AND REMOTE SENSING
(2022)
Article
Computer Science, Hardware & Architecture
Ming Ling, Qingde Lin, Ruiqi Chen, Haimeng Qi, Mengru Lin, Yanxiang Zhu, Jiansheng Wu
Summary: This article proposes a hardware-accelerated implementation of Vina, called Vina-FPGA, that utilizes FPGA to increase the speed and reduce energy consumption in the molecular docking process. Compared to CPU and GPU-accelerated versions, Vina-FPGA shows better performance in terms of speed and energy efficiency.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
(2023)
Article
Engineering, Electrical & Electronic
Riccardo Della Sala, Davide Bellizia, Giuseppe Scotti
Summary: This paper presents a True Random Number Generator (TRNG) implemented using latched-XOR (LX) gates. The proposed TRNG improves the throughput of conventional TRNGs by combining latches metastability and ring oscillators jitter. Experimental results show that the generated bitstreams exhibit good randomness and the TRNG is robust to voltage and temperature variations. The FPGA implementation is compact and efficient, achieving high throughput.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2022)
Article
Engineering, Electrical & Electronic
Chao Chen, Chengyu Liu, Jianqing Li, Bruno da Silva
Summary: This study optimizes the bucket-assisted SampEn algorithm to address its time and space complexity issue, and accelerates it on FPGA through efficient random storage and data access. A scheduling strategy is introduced to handle unbalanced loads. Experimental results show that our approach is effective and practical for measuring time-series complexity.
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT
(2023)
Article
Computer Science, Hardware & Architecture
Lucas Leiva, Jordina Torrents-Barrena, Martin Vazquez
Summary: Reinforcement learning is a method where an agent interacts with the environment to maximize rewards based on sequential decisions. It is widely used in various domains but requires large data processing and computational power. The letter proposes a FPGA-based accelerator for the Markov decision process, achieving over 7x acceleration compared to the original version.
IEEE EMBEDDED SYSTEMS LETTERS
(2023)
Article
Engineering, Biomedical
Kuanchuan Wang, Xinyu Hao, Jiang Wang, Bin Deng
Summary: This study evaluates four commonly used spike encoding algorithms based on FPGA implementation results, including calculation speed, resource consumption, accuracy, and anti-noiseability. By analyzing and comparing the evaluation results, the characteristics and application range of different algorithms are summarized. Finally, a scoring method is proposed for spike coding algorithm selection to improve the encoding efficiency of neuromorphic SNNs.
IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
(2023)
Article
Computer Science, Hardware & Architecture
Teng Wang, Lei Gong, Chao Wang, Yang Yang, Yingxue Gao, Xuehai Zhou, Huaping Chen
Summary: Since Google proposed Transformer in 2017, it has made significant developments in natural language processing (NLP) and also impacted computer vision. This study introduces a novel vision transformer accelerator architecture, ViA, based on FPGA, to efficiently execute Transformer applications and address cost challenges.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2022)
Article
Agronomy
Tomyslav Sledevic, Arturas Serackis, Darius Plonis
Summary: This paper presents an image-based pollen detector for monitoring the status of bee colonies. By training and testing different densities of convolutional neural networks (CNNs), a suitable network for pollen grain detection at the chosen image resolution was identified. A new CNN accelerator architecture was proposed and implemented on a cost-optimized FPGA. The system demonstrated high classification accuracy and frame rate, making it suitable for real-time hive status monitoring.
Article
Automation & Control Systems
Han Xu, Jialin Zheng, Yangbin Zeng, Weicheng Liu, Fuhai Zhao, Chunhui Qu, Zhengming Zhao
Summary: This article introduces a topology-aware matrix partitioning (TA-MP) method for accurate real-time simulation in high-frequency applications. The method uses an implicit numerical algorithm to ensure stability and employs iterative methods to solve implicit equations. By partitioning the PES matrix into blocks with topological meanings and constructing a constant iterative matrix using its constant diagonal blocks, the TA-MP method bypasses the limitations of using iterative methods in real-time simulations. The method eliminates the need to store inverse matrices and only requires matrix-vector multiplications, making it efficient on FPGA.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
(2023)
Article
Engineering, Electrical & Electronic
Zijian Gao, Yuting Shen, Daohuai Jiang, Yuwei Zheng, Fengyu Liu, Feng Gao, Fei Gao
Summary: In this article, we propose a palm-size PA tomography (PAT) system, named palmPAT, for miniaturized low-cost PA imaging with high performance. We implemented a high-quality image reconstruction using field-programmable gate array (FPGA), which can easily adapt to widely used algorithms. In vivo human finger experiments were performed to demonstrate the feasibility and potential of the system. This is the first study focused on the implementation and comparison of three frequently used PA image reconstruction algorithms based on FPGA platform.
IEEE SENSORS JOURNAL
(2023)
Editorial Material
Computer Science, Hardware & Architecture
Christian Pilato, Zhenman Fang, Yuko Hara-Azumi, Jim Hwang
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
(2022)
Article
Green & Sustainable Science & Technology
Kelly M. Kibler, Christian Pilato, Linda J. Walters, Melinda Donnelly, Jyotismita Taye
Summary: This study evaluates the biophysical limitations to mangrove-seedling persistence by measuring the anchoring force of two mangrove species. The study found that the anchoring force of Rhizophora mangle seedlings was consistently higher than Avicennia germinans, but the rate of increase in anchoring force with growth was faster for Avicennia germinans. Increasing the density of surrounding vegetation had a positive effect on the anchoring force of both species.
Article
Computer Science, Hardware & Architecture
Stephanie Soldavini, Karl Friebel, Mattia Tibaldi, Gerald Hempel, Jeronimo Castrillon, Christian Pilato
Summary: This article proposes an automated tool flow for generating massively parallel accelerators on high-bandwidth-memory-equipped FPGAs from a domain-specific language. The method allows designers to integrate and evaluate various compiler or hardware optimizations. Experimental results show that this approach enables efficient data movement and processing, and achieves up to 103 GFLOPS with one compute unit on a Xilinx Alveo U280, which is up to 25x more energy efficient than expert-crafted Intel CPU implementations.
ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS
(2023)
Article
Computer Science, Hardware & Architecture
Christian Pilato, Luca Collini, Luca Cassano, Donatella Sciuto, Siddharth Garg, Ramesh Karri
Summary: The globalization of the electronics supply chain requires effective methods to prevent reverse engineering and IP theft. Logic locking is a promising solution, but there are concerns about overhead and choosing the optimal security metric. This study proposes a metaframework for optimizing behavioral locking during high-level synthesis (HLS) of IP cores, providing better results than random or topological locking.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2023)
Article
Engineering, Electrical & Electronic
Raul Murillo, Alberto A. Del Barrio, Guillermo Botella, Christian Pilato
Summary: This paper introduces a method of incorporating the posit data type into the high-level synthesis design process to improve the computational accuracy for scientific applications. Evaluations show that using posit arithmetic reduces computation errors and achieves higher accuracy compared to standard floating-point numbers. The paper also proposes a hybrid scheme that utilizes posit numbers in private local memory while the accelerator operates in the traditional floating-point notation.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Article
Computer Science, Hardware & Architecture
Mattia Tibaldi, Christian Pilato
Summary: This article provides a survey of academic literature on field programmable gate array (FPGA) and their utilization for energy efficiency acceleration in data centers. It critically presents existing FPGA energy optimization techniques and discusses their application in such systems. The article also analyzes over ten years of research in energy optimization techniques, classifying them by purpose, method of application, and impacts on consumption sources. Finally, the article concludes with the challenges and potential innovations in this sector.
IEEE TRANSACTIONS ON SUSTAINABLE COMPUTING
(2023)
Proceedings Paper
Automation & Control Systems
Nadia Ibellaatti, Edouard Lepape, Alp Kilic, Kaya Akyel, Kassem Chouayakh, Fabrizio Ferrandi, Claudio Barone, Serena Curzel, Michele Fiorito, Giovanni Gozzi, Miguel Masmano, Ana Risquez Navarro, Manuel Munoz, Vicente Nicolau Gallego, Patricia Lopez Cueva, Jean-noel Letrillard, Franck Wartel
Summary: European efforts to enhance competitiveness in space services involve research and development of advanced software and hardware solutions. The EU-funded HERMES project contributes by qualifying radiation-hardened, high-performance programmable microprocessors and developing a software ecosystem for complex applications. Its objectives include reaching a technology readiness level of 6 for the rad-hard NG-ULTRA FPGA, and validating tools supporting multicore software programming and FPGA acceleration.
2023 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE
(2023)
Proceedings Paper
Automation & Control Systems
Chao Lu, Christian Pilato, Kanad Basu
Summary: In recent years, there has been a rise in the number of quantum algorithms, which offer exponential speedup compared to classical algorithms. Quantum algorithms have applications in machine learning, molecular simulation, and cryptography. However, programming a quantum computer requires extensive knowledge of linear algebra and quantum mechanics, which may be challenging for traditional software programmers. Additionally, the current quantum programming paradigm lacks scalability and integration of quantum circuits for complex functionality. This paper introduces QHLS, the first quantum high-level synthesis (HLS) framework, which allows quantum programmers to start with high-level behavioral descriptions and automatically generate corresponding quantum circuits, reducing the complexity of quantum computer programming. Experimental results demonstrate the success of QHLS in translating high-level behavioral software programs containing arithmetic, logical, and conditional statements.
2023 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE
(2023)
Proceedings Paper
Automation & Control Systems
Vito Giovanni Castellana, Nicolas Bohm Agostini, Ankur Limaye, Vinay Amatya, Marco Minutoli, Joseph Manzano, Antonino Tumeo, Serena Curzel, Michele Fiorito, Fabrizio Ferrandi
Summary: The opensource Software Defined Architectures (SODA) Synthesizer is a compiler-based tool that automatically generates domain-specialized systems for ASICs or FPGAs from high-level programming. It consists of a frontend, SODA-OPT, which interfaces with productive programming tools and performs high-level optimizations, and a state-of-the-art high-level synthesis backend, Bambu, to generate custom accelerators. One specific application of SODA is the generation of accelerators for ultra-low latency inference and control on autonomous systems for scientific discovery.
2023 28TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC
(2023)
Proceedings Paper
Automation & Control Systems
Stephanie Soldavini, Donatella Sciuto, Christian Pilato
Summary: Optimizing data movements is crucial in dealing with the challenges of data deluge and big data applications in heterogeneous computing. Although modern high-level synthesis (HLS) tools are efficient in optimizing computational aspects, there is still room for improvement in data transfers. Novel architectures, such as High-Bandwidth Memory with wider data busses, have been developed to address this issue. However, designers need to tailor their hardware/software interfaces to fully utilize the available bandwidth. We propose a methodology that automates the discovery and implementation of a data layout to maximize the available bandwidth when streaming data between memory and an accelerator.
2023 28TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC
(2023)
Proceedings Paper
Computer Science, Artificial Intelligence
Aritra Sarkar, Zaid Al-Ars, Koen Bertels
Summary: In this research, the universal reinforcement learning agent models are extended to quantum environments. The utility function of a classical exploratory stochastic Knowledge Seeking Agent is generalized to distance measures from quantum information theory. Quantum process tomography algorithms are used to model environmental dynamics. The optimal policy is selected based on a mutable cost function, and multiple agents with pareto-optimal policies evolve using genetic programming.
ARTIFICIAL GENERAL INTELLIGENCE, AGI 2022
(2023)
Proceedings Paper
Computer Science, Hardware & Architecture
Serena Curzel, Sofija Jovic, Michele Fiorito, Antonino Tumeo, Fabrizio Ferrandi
PROCEEDINGS OF THE 2022 31ST INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PACT 2022
(2022)
Proceedings Paper
Computer Science, Artificial Intelligence
Dominik Sisejkovic, Luca Collini, Benjamin Tan, Christian Pilato, Ramesh Karri, Rainer Leupers
Summary: This paper investigates the resilience of the state-of-the-art RTL locking method ASSURE against machine-learning attacks. Two machine-learning reinforced RTL locking schemes are proposed based on the lessons learned. ML-driven security metrics are also developed to evaluate the schemes against the latest ML-based attacks.
PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC 2022
(2022)
Proceedings Paper
Computer Science, Artificial Intelligence
Chiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato
Summary: Fabricating integrated circuits is becoming too expensive for many semiconductor design companies. To protect the intellectual property of hardware designs, designers can use embedded reconfigurable devices to hide the true functionality of selected design portions, and the ALICE design flow addresses the challenges of this process.
PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC 2022
(2022)
Proceedings Paper
Computer Science, Theory & Methods
Nicolas Bohm Agostini, Ankur Limaye, Marco Minutoli, Vito Giovanni Castellana, Joseph Manzano, Antonino Tumeo, Serena Curzel
Summary: The SODA Synthesizer is an open-source hardware compiler framework that consists of a frontend and a backend. The MLIR-based frontend performs system-level design, code partitioning, and high-level optimizations, while the backend uses a state-of-the-art high-level synthesis tool to generate the final hardware design. The framework can interface with logic synthesis tools for field programmable gate arrays or application-specific integrated circuits, both commercial and open-source.
2022 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, ICCAD
(2022)
