Article
Engineering, Electrical & Electronic
Sigang Ryu, Chan Young Park, Wooryeol Kim, Seuk Son, Jaeha Kim
Summary: This paper introduces a new time-based pipelined ADC with MDAC stages capable of robust 2x residue amplification. The ADC does not require amplifiers, making it suitable for low-voltage digital processes. The prototype 10-bit ADC fabricated in 28nm CMOS demonstrates excellent performance with high FOM.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2021)
Article
Computer Science, Information Systems
Jihyun Baek, Juyong Lee, Jintae Kim, Hyungil Chae
Summary: This paper presents a pipelined noise-shaping SAR ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter.
Article
Engineering, Electrical & Electronic
Weibo Hu, Xiang Yan, Haitao Cui, Jingbin Feng, Yi Hu, Jiali Hou, Zhenguo Li, Chao Lu, Zhiming Xiao, Wei Ma
Summary: A GM-R amplifier is proposed as a residual amplifier for a 16-bit two-stage non-pipelined ADC in intermittent signal acquisition applications. It utilizes resistor ratios to generate constant gain and provides a solution for small input amplitudes and wide temperature ranges. The input circuit consists of source followers and a bridge resistor to convert residual voltages to currents. The design prototype achieved high SNR, SNDR, THD, and low DNL and INL after calibration.
MICROELECTRONICS JOURNAL
(2023)
Article
Computer Science, Information Systems
Juyong Lee, Seungjun Lee, Kihyun Kim, Hyungil Chae
Summary: The study proposed a PLNS-SAR ADC structure with a ring amplifier to achieve high resolution, low power consumption, and noise suppression. With processing of residual signals and high-gain ring amplifier, a SNDR of 70 dB and a FoM(S)(,)(SNDR) of 163.5 dB were achieved in the implementation.
Article
Computer Science, Information Systems
Shuang Xie, Yong Wang
Summary: This paper presents a digital calibration method for a 10-bit noise-shaping SAR ADC. The proposed method achieves a similar INL and 1.3 dB better SNR compared to the traditional DWA method without oversampling. It also saves 50% power and occupies a small active area in the fabrication process.
Article
Engineering, Electrical & Electronic
Sein Oh, Younggyun Oh, Juyong Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae
Summary: The pipelined noise-shaping successive approximation register (NS-SAR) ADC with 1-2 multistage noise-shaping (MASH) structure achieves high resolution and wide bandwidth while greatly relaxing the design requirements of each SAR quantizer, resulting in good power efficiency.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2021)
Article
Computer Science, Hardware & Architecture
Chao Cao, Haijun Guo
Summary: This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. The prototype exhibits excellent performance with high figure of merit, effective number of bits, and dynamic range.
INTEGRATION-THE VLSI JOURNAL
(2022)
Article
Computer Science, Information Systems
Jingchao Lan, Danfeng Zhai, Yongzhen Chen, Zhekan Ni, Xingchen Shen, Fan Ye, Junyan Ren
Summary: This paper presents a 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC in 28-nm CMOS, utilizing a bias-enhanced ring amplifier, high linearity front-end design, and calibration techniques to achieve competitive performance at 250 MHz input frequency. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, with a FoM(w) of 0.48 pJ/conv.-step.
Article
Engineering, Electrical & Electronic
Yuefeng Cao, Shumin Zhang, Tianli Zhang, Yongzhen Chen, Yutong Zhao, Chixiao Chen, Fan Ye, Junyan Ren
Summary: This paper introduces a single-coarse dual-fine ADC architecture to enhance energy-efficiency by optimizing quantization and residue generation processes. The proposed digital background calibration and dynamic amplifier further improve performance, leading to significant enhancements in signal-to-noise ratio and distortion characteristics in measurement.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2021)
Article
Computer Science, Information Systems
Junlong Tang, Yaodong Wang, Hongbo Gu, Wanghui Zou
Summary: A novel self-calibration comparator for a 12-bit 2.5 MSPS SAR ADC applied in a touch MCU with small area, high precision, fast response speed, and low-voltage detection is proposed in this paper. It employs a combination of IOS/OOS and an offset trimming circuit to reduce the offset of the cascade preamplifier and OTA, and a 5-bit digital controller is designed to further reduce residual offset voltage. The self-calibration technology compensates the conversion error in the SAR ADC system to a minimum.
Article
Engineering, Electrical & Electronic
Ali Pourahmad, Rasoul Dehghani, Seyed Amir-Reza Ahmadi-Mehr, Reza Lotfi
Summary: This study presents an innovative DAC-less SAR ADC architecture that uses a binary search algorithm to emulate the DAC function, overcoming the limitations of conventional DAC implementations. The hardware implementation of this architecture is less complex and more robust against PVT variations, while still being able to adapt to different sampling rates and resolutions.
MICROELECTRONICS JOURNAL
(2022)
Article
Engineering, Electrical & Electronic
Hyunchul Yoon, Changuk Lee, Taewoong Kim, Yigi Kwon, Youngcheol Chae
Summary: This article introduces a PVT-robust capacitively degenerated dynamic amplifier as the residue amplifier of the low-power pipelined SAR ADC. The proposed dynamic amplifier achieves a voltage gain of 16 and high linearity over a wide temperature range with an on-chip timing generator. The prototype ADC achieves a high SNDR and SFDR while consuming low power and showing minimal variations in SNDR.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2023)
Article
Engineering, Electrical & Electronic
Yan Song, Yan Zhu, Chi-Hang Chan, Rui P. Martins
Summary: This article introduces a SAR-assisted NS ADC incorporating various techniques to improve performance, such as using a dynamic amplifier for residue amplification and error feedback to achieve 1st-order NS. Additionally, an extra residue feed-forward path is introduced to compensate for NTF deterioration caused by gain mismatch.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2021)
Article
Computer Science, Information Systems
Min-Jae Seo
Summary: This work introduces a novel 12-bit 200 MS/s dual-residue pipelined SAR ADC with a single open-loop residue amplifier, eliminating the need for inter-stage gain-matching calibration. It sequentially generates two residue levels to convert and proposes a capacitive interpolating SAR ADC. The prototype ADC achieves high performance metrics without inter-stage mismatch calibration.
Article
Computer Science, Information Systems
Chong-Cheng Huang, Guo-Ming Sung, Xiong Xiao, Shan-Hao Sung, Chao-Hung Huang
Summary: This paper presents a multichannel dual-mode SAR ADC designed for brushless DC motor drive, with advantages of low power consumption and high resolution achieved through the use of dual-mode sampling.
Article
Computer Science, Hardware & Architecture
Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak, Rui P. Martins
Summary: This article presents a low-jitter and low-spur type-II sampling phase-locked loop (S-PLL). The introduction of a differential parallel-series double-edge sampling phase detector (S-PD) achieves a high phase-detection gain and reduces the S-PLL in-band phase noise (PN). The proposed S-PLL, implemented in a 65-nm CMOS, operates at 3.6 GHz and has an integrated jitter of 43.1 fsrms integrated from 1 kHz to 100 MHz, as well as a jitter-power figure-of-merit (FOM) of -258.7 dB. The measured reference (REF) spur is -80.34 dBc at f(REF) and -75.17 dBc at 2 f(REF), respectively.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
(2023)
Article
Engineering, Electrical & Electronic
Lin Wang, Yong Chen, Chaowei Yang, Xionghui Zhou, Mei Han, Crovetti Paolo Stefano, Pui-In Mak, Rui P. Martins
Summary: This paper presents a bang-bang clock and data recovery circuit (BBCDR) that has an ultra-wide capture range. The circuit achieves automatic frequency capture and phase locking over a wide range without using a frequency detector, thanks to a deliberate-current-mismatch technique. Additionally, the circuit accurately obtains an eight-phase clock across the entire frequency range through analog interpolation of quadrature signals. A 65-nm prototype of the BBCDR has been developed, which occupies an area of 0.07 mm(2) and achieves a bit error rate of less than 10(-12) under continuously variable input frequency, with a power consumption of 24.6 mW, resulting in an energy efficiency of 0.769 pJ/bit.
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
(2023)
Review
Computer Science, Information Systems
Yi Chen Lee, Harikrishnan Ramiah, Alexander Choo, Kishore Kumar Pakkirisami Churchill, Nai Shyan Lai, Chee Cheow Lim, Yong Chen, Pui-In Mak, Rui P. Martins
Summary: This paper reviews and explores the alternative approach of a multiband RF energy-harvesting front-end system, which covers all essential circuitry. It aims to fill the research gap in the further advancement of multiband RF energy harvesting towards enhancing its performance through optimal circuit integration of the front-end system.
Article
Computer Science, Information Systems
Ya-Jie Wu, Ricardo Brito, Wai-Hei Choi, Chi-Seng Lam, Man-Chung Wong, Sai-Weng Sin, Rui Paulo Martins
Summary: Smart meter monitors electricity consumption through modern metering devices connected to the IoT, providing intelligent and fast applications like arc fault protection based on nonintrusive monitoring load classification with fast safety responses. Traditional IoT architecture cannot support such fast responses under loading variation.
IEEE INTERNET OF THINGS JOURNAL
(2023)
Article
Engineering, Electrical & Electronic
Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui P. Martins
Summary: This paper presents a BBCDR circuit, which is a reference-less and frequency-detector-less single-loop bang-bang clock and data recovery circuit, with the feature of wide frequency acquisition. The circuit uses a current-starved ring oscillator controlled by a 5-bit resistive digital-to-analog converter for quarter-rate operation, achieving a capture range of 110.4%. By utilizing a deliberate-current-mismatch charge pump pair, the circuit eliminates power-hungry circuits and adopts a single-sided capture scheme in the frequency detection characteristic. With a hybrid control circuit, the proposed BBCDR automates frequency acquisition and phase tracking in 32 bands. Implementing this circuit in a 65-nm CMOS, the BBCDR covers a broad data rate range from 10.8 to 37.4 Gb/s, achieving high acquisition speed and energy efficiency.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Review
Engineering, Electrical & Electronic
Xuchu Mu, Guangshu Zhao, Anyang Zhao, Yang Jiang, Man-Kay Law, Makoto Takamiya, Pui-In Mak, Rui P. Martins
Summary: This paper presents the design challenges and advanced circuit techniques of integrated gate drivers for non-isolated buck converters using gallium nitride (GaN) devices. The techniques discussed aim to achieve fast switching and high conversion efficiency by addressing various performance aspects, such as bootstrapping enhancement, prevention of over-voltage and false-switching, EMI noise suppression, and adaptive driving optimization.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Article
Engineering, Electrical & Electronic
Zihan Yang, Mo Huang, Yan Lu, Rui P. Martins
Summary: This article introduces a method for relative stability analysis in multi-loop systems. The conventional open-loop based method may not be accurate for multi-loop systems, while the proposed method can more accurately find breaking points and has been verified to be effective.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2023)
Article
Engineering, Electrical & Electronic
Junlin Zhong, Xiaofeng Yang, Rui P. Martins, Yan Zhu, Chi-Hang Chan
Summary: This brief presents a compact and power-efficient full ring-oscillator (RO)-based cascaded fractional-N PLL. The proposed PLL prototype achieves a 686 fs integrated rms jitter at a 4 GHz output frequency, while consuming 10.21mW. The BMS scheme is introduced to improve the phase noise of the frequency multiplier.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2023)
Article
Engineering, Electrical & Electronic
Xiangyu Mao, Yan Lu, Rui P. Martins
Summary: This brief presents a 1A fully-integrated switching LDO for digital loads, featuring a 4-phase 200MHz PWM to reduce output ripple and allow for a smaller output capacitor. The design incorporates a single feedback loop with a wide bandwidth error amplifier for improved dynamic voltage scaling and reduced transient recovery time. The use of a single PMOS with auxiliary constant current control reduces the power transistor size and driver current significantly.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2023)
Article
Computer Science, Information Systems
Chongyao Xu, Litao Zhang, Man-Kay Law, Xiaojin Zhao, Pui-In Mak, Rui P. Martins
Summary: This article presents an obfuscated-interconnection physical unclonable function (OIPUF) to resist modeling attacks, and proposes a metastability-detection (MD) arbiter to improve the reliability. The experimental results demonstrate the effectiveness of the proposed method in enhancing security and reliability while achieving high prediction accuracy using machine learning algorithms.
IEEE INTERNET OF THINGS JOURNAL
(2023)
Article
Engineering, Electrical & Electronic
Qiaobo Ma, Xiongjie Zhang, Anyang Zhao, Huihua Li, Yang Jiang, Man-Kay Law, Makoto Takamiya, Rui P. Martins, Pui-In Mak
Summary: This work proposes a high-step-down switched-capacitor hybrid DC-DC converter that effectively addresses the conduction loss in the inductor and power switches. The converter achieves superior performance in reducing the inductor DC current compared to existing converters, and enhances efficiency and on-chip power/current density. It is capable of regulating an output voltage within a certain range and accommodates different input voltages.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Article
Engineering, Electrical & Electronic
Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Rui Paulo Martins, Yan Zhu, Jan Craninckx, Chi-Hang Chan
Summary: This paper presents a 12-bit, 1-GS/s SAR-assisted pipeline ADC with background distortion and split-ADC-like gain calibrations. The ADC uses calibration to tackle distortion and achieve adequate linearity. A low-cost auxiliary channel is introduced for reference and gain calibration. The digital post-distortion filter coefficients are optimized using a multi-step multi-layer LMS algorithm. The calibrated ADC achieves high SNDR and SFDR with low power consumption.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Article
Engineering, Electrical & Electronic
Caolei Pan, Chenchang Zhan, Rui P. Martins, Chi-Seng Lam
Summary: This paper presents a high-efficiency continuous-output-current buck-boost converter with a single mode operation. The proposed converter allows continuous delivery of output current while achieving a wide conversion ratio range and exhibits small output voltage ripple, good transient response, and high efficiency. A double clock timing control method is employed for smooth controller-mode transition.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Article
Engineering, Electrical & Electronic
Hongzhi Zhao, Minglei Zhang, Yan Zhu, Rui P. Martins, Chi-Hang Chan
Summary: This article presents a high-speed ADC converter that achieves high conversion speed and resolution bandwidth using a linearized configurable V2T buffer and TD quantization. By configuring the TD-FS input, the accuracy requirement of the quantizer is reduced, and the nonlinearity of the buffer is suppressed using a compensation scheme. The experimental results demonstrate the good performance and power efficiency of this prototype.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2023)
Article
Engineering, Electrical & Electronic
Hongshuai Zhang, Yan Zhu, Rui P. Martins, Chi-Hang Chan
Summary: This article presents a second-order noise shaping pipelined successive approximation register analog-to-digital converter with fully passive noise shaping and a second-order gain error shaping based on a Quantization Prediction-Unrolled scheme. The ADC achieves high performance in terms of signal-to-noise-and-distortion ratio and consumes low power.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2023)
