4.6 Article

0.5T0.5R-An Ultracompact RRAM Cell Uniquely Enabled by van der Waals Heterostructures

Journal

IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 68, Issue 4, Pages 2033-2040

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2021.3057598

Keywords

1T1R; 2-D-FET; 3-D-integration; graphene; h-BN; in-memory computing; memristor; neural circuit; neuromorphic computing; plasticity; RRAM; smart transistor; switching-energy; switching-speed; synapse; transition metal di-chalcogenide; van derWaals (vdW) materials; WS2

Funding

  1. ARO [W911NF1810366]
  2. AFOSR (DURIP) [FA9550-18-1-0448]
  3. JST CREST [SB180064]
  4. UC MRPI Research Program [MRP-17-454999]

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This study presents a novel memory architecture that combines 1T and 1R into a single hybrid device by leveraging lateral and vertical van der Waals heterostructures, overcoming the integration density limitation of conventional RRAM cells. The 0.5T0.5R memory cell achieved record performance, low energy consumption, small footprint, long retention, and high endurance, making it a promising candidate for neuromorphic and in-memory computing applications.
Conventional designs of the extensively studied resistive-random access-memory (RRAM) cell involve one transistor and one RRAM-1T1R, i.e., two separate devices thereby constraining its integration density. In this work, we overcome this longstanding limitation by experimentally demonstrating a novel memory architecture that combines the 1T and 1R into a single hybrid device by uniquely leveraging both lateral and vertical van der Waals (vdW) heterostructures. This ultracompact device, which can be considered as a 0.5T0.5R memory cell, reduces the device count by half-the first of its kind in RRAM technology history, and simultaneously allows higher lateral aswell as vertical (3-D) integration density w.r.t. the conventional 1T1R architecture. The unique smart device that can retain information after power is turned off is structurallydesigned by utilizing a shared graphene edge-contact and resistively switchable hexagonal boron nitride (h-BN) insulator. Aided by design optimization, record performance (<10 ns switching-speed), energy-(similar to 0.07 pJ/bit), and area-efficiency (smallest footprint among all reported vdW-material-based RRAM memory units), as well as great retention (10(6) s) and endurance (>1000), benchmarked against current vdW-material-based RRAM devices, have been achieved by this 0.5T0.5R memory cell. Moreover, the RRAM's fine tunability with ultrashort pulsewidth, pulse amplitude, and gate voltage, enables synaptic plasticity and makes it an integrated three-terminal RRAM with considerable potential for neuromorphic and in-memory computing applications.

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