Article
Computer Science, Hardware & Architecture
Morgana Macedo Azevedo da Rosa, Patricia Ucker da Costa, Eduardo Antonio Cesar da Costa, Sergio J. M. Almeida, Guilherme Paim, Sergio Bampi
Summary: This study proposes a low power dissipation VLSI hardware architecture for interference canceling in biopotential signals. By utilizing optimized hardware architectures and efficient arithmetic operations, the proposed approach achieves low latency and power-efficient performance. The experimental results demonstrate its effectiveness in suppressing interferences in various biopotential signals, and its superiority in terms of circuit area and power dissipation compared to existing solutions.
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
(2022)
Article
Telecommunications
K. Gavaskar, R. Dhivya, R. Dimple Dayana
Summary: The performance of VLSI circuits depends on their design architecture, and designing a power-efficient device is the main challenge. The Phase Lock Loop (PLL) plays a significant role in telecommunications applications, and achieving a high operating frequency with minimal power consumption is the main concern. This study proposes a PLL design that reduces power consumption by minimizing the Phase Frequency Detector's power consumption, resulting in a 3% decrease compared to existing designs. Additionally, the proposed design has lower time delay and PDP, making it a viable circuit for high-performance PLL systems.
WIRELESS PERSONAL COMMUNICATIONS
(2022)
Article
Computer Science, Artificial Intelligence
V Govindaraj, B. Arunadevi
Summary: The study introduces a method for estimating the power of CMOS VLSI circuits using machine learning, specifically the random forest algorithm, which is optimized by the multiobjective NSGA-II algorithm. Experimental results demonstrate the high accuracy and effectiveness of the random forest method in power estimation for CMOS VLSI circuits.
APPLIED ARTIFICIAL INTELLIGENCE
(2021)
Article
Engineering, Electrical & Electronic
Vinay Chakravarthi Gogineni, Ramesh Sambangi, Daney Alex, Subrahmanyam Mula, Stefan Werner
Summary: This paper attempts to implement the RFF-based kernel least mean square (RFF-KLMS) algorithm on hardware for the first time. Several computationally expensive feature functions are reformulated for real-time VLSI implementation. The synthesized delayed RFF-KLMS architectures require minimal hardware increase while significantly improving estimation performance for the nonlinear model.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Article
Computer Science, Interdisciplinary Applications
Dobromir P. Dobrev, Tatyana D. Neycheva
Summary: This paper presents a powerful solution for eliminating power-line interference using a mixed analog-digital approach. The approach automatically balances the impedance bridge and cancels interference by adding common-mode voltage to the differential biosignal.
MEDICAL & BIOLOGICAL ENGINEERING & COMPUTING
(2022)
Article
Engineering, Electrical & Electronic
Sandeep Narasapura Ramesh, Abbas Semnani
Summary: This article introduces a novel plasma-based frequency-selective limiter (FSL) technology, which combines an absorptive bandstop filter topology with a plasma coupling structure. The design includes two signal paths: one through a delay line and the other through two coupled resonators with a plasma cell. The theory of this plasma FSL is developed and evaluated using coupled transmission line theory. The fabricated prototype demonstrates high selectivity, isolation, and efficiency.
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
(2023)
Article
Computer Science, Information Systems
Piotr Baryczkowski, Sebastian Szczepaniak, Natalia Matykiewicz, Kacper Perz, Szymon Szczesny
Summary: This article discusses the complexity of semiconductor implementation of TinyML edge systems, specifically analyzing the influence of model parameters on system complexity. A CMOS preprocessor device is used as a case study for heart rate detection, utilizing current and weak inversion operating modes. The study analyzes the impact of tuning hyperparameters in the learning process on the performance of the final device, and explores the relationships between model parameters, input data parameters, and CMOS circuit parameters.
Article
Automation & Control Systems
C. Kalamani, S. Kamatchi, S. Sasikala, L. Murali
Summary: An adaptive filter is a crucial filter used in statistical signal processing, with LMS algorithm being widely used to remove noise from ECG signals. Adaptive filters can be implemented in DSPs or VSPs. The article also presents a folded adaptive lattice LMS filter algorithm, which reduces hardware usage and is effective in removing power line interference noise from ECG signals. The folded architecture achieved significant area reduction of 82.60% and 91.05% for K = 2 and K = 4, respectively, compared to a normal adaptive lattice filter.
Article
Engineering, Biomedical
Sahar Amini, Behzad Mozaffari Tazehkand
Summary: This paper investigates different types of notch filters and proposes a simple time-variant method to improve filter performance. The method can more efficiently reduce transient duration while achieving narrow bandwidth. Simulation results show that the proposed algorithm can enhance the performance of feedback-structured filters compared to other methods.
BIOMEDICAL SIGNAL PROCESSING AND CONTROL
(2022)
Article
Engineering, Electrical & Electronic
Seyyed-Amir Ayati, Amirreza Alizadeh, Sayfe Kiaei
Summary: The full-duplex transceiver with on-chip self-interference-cancellation (SIC) achieves 110 dB of SIC through three stages: RF front-end hybrid, baseband analog, and baseband digital. The integrated hybrid in the RF front-end utilizes an adaptive tuning impedance network to track antenna impedance variations and achieve over 50 dB of SIC. N-path mixer-first architecture is used for the receiver to improve linearity and provide out of band blocker cancellation. Through analog and digital self-interference cancellation, the total SIC of the hybrid and TIC exceeds 70 dB thanks to adaptive gradient descent algorithm.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2021)
Article
Public, Environmental & Occupational Health
Bin-qiang Chen, Bai-xun Zheng, Chu-qiao Wang, Wei-fang Sun
Summary: An adaptive sparse detector is proposed in this study to reduce powerline interference (PLI) in EEG signal acquisition. By utilizing sparse representation and an overcomplete dictionary, the detector optimizes representation coefficients to reduce PLI interference on EEG features effectively.
FRONTIERS IN PUBLIC HEALTH
(2021)
Article
Engineering, Electrical & Electronic
Jongheun Lee, Juseop Lee
Summary: This article discusses a method for designing a reflectionless bandstop filter that has high performance, including exceptional impedance matching, extended upper passband, and simplified design structure.
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
(2021)
Article
Engineering, Electrical & Electronic
Yangyi Zhang, Xianglong Wang, Gang Shi, Zizhao Peng, Lei Chen, Fengwei An
Summary: This paper proposes an AAACA algorithm for demosaicing the Bayer pattern and a resource-efficient VLSI architecture. The algorithm includes an anti-aliasing approach and a color artifacts filter. Experimental results show that the proposed algorithm can significantly remove visual aliasing and color artifacts.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Proceedings Paper
Computer Science, Hardware & Architecture
Morgana da Rosa, Patricia da Costa, Eduardo da Costa, Sergio Almeida, Guilherme Paim, Sergio Bampi
Summary: This work proposes a low power dissipation VLSI hardware architecture for a robust power line interference canceling (PLIC). By combining optimized adaptive filters LMS and HG's hardware architecture, the PLIC VLSI structure effectively suppresses interferences in both ECG and EEG signals, with significant power and area savings compared to the state-of-the-art solution.
34TH SBC/SBMICRO/IEEE/ACM SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI 2021)
(2021)
Article
Engineering, Electrical & Electronic
Vijay Kumar Sharma
Summary: In this paper, a circuit-level reliable low leakage design methodology is proposed for integrated circuits. The proposed approach reduces leakage power significantly and improves the reliability of the circuits, as demonstrated through simulations and comparative experiments.
IETE JOURNAL OF RESEARCH
(2023)
Article
Engineering, Electrical & Electronic
Morgana M. A. da Rosa, Eduardo A. C. da Costa, Leandro Giacomini Rocha, Guilherme Paim, Sergio Bampi
Summary: This paper presents a new radix-2(m) squarer unit that is in demand for a variety of applications, showing higher energy savings compared to other units.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
(2023)
Article
Engineering, Electrical & Electronic
Pedro Taua Lopes Pereira, Guilherme Paim, Eduardo Antonio Cesar da Costa, Sergio Jose Melo de Almeida, Sergio Bampi
Summary: This paper proposes a reconfigurable datapath architecture, ReAdapt, for scaling the energy-quality trade-off of adaptive filtering at runtime. The architecture dynamically selects different levels of filter algorithms complexity and achieves a compact hardware implementation by reusing common modules. Experimental results demonstrate a balanced trade-off between energy and quality, and the dynamic reconfiguration at runtime outperforms the conventional static mode for different signal-to-noise ratio levels.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Article
Engineering, Electrical & Electronic
Pedro Taua Lopes Pereira, Patricia Ucker Leleu da Costa, Guilherme da Costa Ferreira, Brunno Alves de Abreu, Guilherme Paim, Eduardo Antonio Cesar da Costa, Sergio Bampi
Summary: This paper presents a comprehensive design space exploration for improving the energy efficiency of a fast Fourier transform (FFT) VLSI accelerator. It explores the use of approximate multipliers (AxMs) and approximate adder (AxA) circuits to achieve energy savings without significant quality degradation in spectrogram generation. The results show that the LoBA multiplier, together with specific approximation levels for the adder circuits, can achieve the highest energy savings while maintaining the quality of the spectrogram.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2022)
Article
Engineering, Electrical & Electronic
Gerson Andrade, Matheus Silva, Cinthia Schneider, Guilherme Paim, Sergio Bampi, Eduardo Costa, Alexandra Zimpeck
Summary: This brief examines the robustness of the 3-2 AC against process, voltage, and temperature (PVT) variations in a predictive ASAP7 7nm FinFET technology. The impact of these variations on delay, power, and product-delay-power (PDP) of the 3-2 AC in super- and near-threshold voltage operating regimes is evaluated. The results show that process variation is the main concern, with near-threshold operation having a more severe level of variability.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2023)
Article
Computer Science, Hardware & Architecture
Morgana Macedo Azevedo da Rosa, Guilherme Paim, Patricia Ucker Leleu da Costa, Eduardo Antonio Cesar da Costa, Rafael Soares, Sergio Bampi
Summary: Addition units are widely used in error-tolerant applications and serve as building blocks for various math operations. Parallel prefix adders (PPAs) are among the fastest adders due to their optimization of carry generation and propagation. This research introduces approximate PPAs and compares them with energy-efficient approximate adders, showing improved energy-quality and area-quality results.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
(2023)
Article
Engineering, Electrical & Electronic
Brunno Alves de Abreu, Albi Mema, Simon Thomann, Guilherme Paim, Paulo Flores, Sergio Bampi, Hussam Amrouch
Summary: This study develops CMOS-compatible compact majority (MAJ) and minority (MIN) logic gates using the body biasing feature in fully depleted silicon on insulator (FDSOI) technology. The proposed MAJ/MIN gates require considerably fewer transistors compared to their CMOS counterparts. Previous research on using MAJ/MIN gates for logic synthesis has been limited due to their large area requirement when implemented with conventional standard cells. In contrast, the FDSOI-based MAJ/MIN gates in this study leverage mature CMOS commercial technologies. SPICE simulations and error injection analysis demonstrate that MAJ/MIN-based circuits exhibit excellent resilience against errors, making them suitable for safety-critical applications where reliability is crucial.
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS
(2023)
Proceedings Paper
Computer Science, Interdisciplinary Applications
Morgana M. A. da Rosa, Patricia da Costa, Guilherme Paim, Eduardo da Costa, Rafael Soares, Sergio Bampi
Summary: Approximate computing is applied in the calibration procedure for radio astronomy called StEFCal to maximize area and energy savings. The StEFCal circuit uses various approximate arithmetic operators to achieve a trade-off between quality and efficiency. The results demonstrate that combining AxRSU with the NR divider significantly improves the Mean Square Error (MSE) and achieves substantial energy savings compared to the state-of-the-art.
2023 IEEE 14TH LATIN AMERICA SYMPOSIUM ON CIRCUITS AND SYSTEMS, LASCAS
(2023)
Proceedings Paper
Computer Science, Interdisciplinary Applications
Jiovana Sousa Gomes, Tulio Pereira Bitencourt, Sergio Bampi, Fabio Luis Livi Ramos
Summary: Video processing is necessary in today's society due to the wide consumption of video content. Video coding formats or standards are used to handle the large amount of data generated. The AV1 format is a recent alternative that efficiently encodes video and aims to be royalty-free. This paper introduces a novel Multi-Boolean Approach for the AV1 Arithmetic Decoder design, which involves processing multiple Boolean symbols in parallel to improve throughput. An analysis of different hardware architectures is conducted, and it is concluded that the best trade-off choice is to use two Boolean symbols in parallel with a multicycle AV1 arithmetic decoder circuit.
2023 IEEE 14TH LATIN AMERICA SYMPOSIUM ON CIRCUITS AND SYSTEMS, LASCAS
(2023)
Proceedings Paper
Computer Science, Interdisciplinary Applications
Morgana M. A. da Rosa, Guilherme Paim, Henrique B. Seidel, Sergio Almeida, Eduardo A. C. da Costa, Sergio Bampi
Summary: In this study, an approximate level-3 Haar wavelet transform method is proposed for ECG signal processing. Compared to the exact transform, this method significantly reduces energy consumption and VLSI hardware area while improving R-peak detection accuracy. Our method outperforms the state-of-the-art approximate level-4 Haar wavelet transform in terms of power dissipation and hardware area.
PROCEEDINGS OF THE 2022 15TH IEEE DALLAS CIRCUITS AND SYSTEMS CONFERENCE (DCAS 2022)
(2022)
