Ultra-Compact High-Speed Polarization Division Multiplexing Optical Receiving Chip Enabled by Graphene-on-Plasmonic Slot Waveguide Photodetectors

Polarization multiplexing technology is widely adopted for increasing the capacity in optical communication systems. Especially, silicon-based integrated polarization division multiplexing (PDM) optical receivers with large bandwidth therein play an important role, which are crucial for on-chip large-capacity optical interconnection. Here, a silicon-based PDM optical receiving chip is enabled by two-dimensional grating couplers and graphene-on-plasmonic slot waveguide photodetectors. Utilizing the advantages of the designed focusing two-dimensional grating couplers and plasmonic-slot-waveguide-enhanced graphene-light interaction, the optical receiving chip is achieved with an ultra-small footprint, a bandwidth exceeding 70 GHz and a reception of PDM signals in a line rate of 128 Gbit s(-1) non-return-to-zero and 224 Gbit s(-1) four-level pulse-amplitude-modulation at 1550 nm, accompanied by the bit error rates lower than the KP4 forward error correction threshold and 15% soft-decision forward error correction threshold, respectively. Comparing with receiving the single-polarization state, simultaneous receiving dual-polarization state introduces about 1 dB additional power penalty because of inter-polarization crosstalk. The graphene-plasmonic PDM optical receiving chip can greatly improve the line rate of the system, showing its unique advantages of small footprint, high speed, large bandwidth, low crosstalk and complementary metal-oxide-semiconductor compatibility, which can be potentially used in the next generation silicon-based high-speed optical communication.

Automated summary

This study introduces a silicon-based PDM optical receiving chip using two-dimensional grating couplers and graphene-on-plasmonic slot waveguide photodetectors. The chip features an ultra-small footprint, bandwidth exceeding 70 GHz, and reception of PDM signals at high line rates. It shows potential for improving system line rates with unique advantages such as small footprint, high speed, large bandwidth, low crosstalk, and CMOS compatibility.