4.6 Article Proceedings Paper

Gallium Nitride and Silicon Transistors on 300 mm Silicon Wafers Enabled by 3-D Monolithic Heterogeneous Integration

Journal

IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 67, Issue 12, Pages 5306-5314

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2020.3034076

Keywords

300 mm silicon; 3-D monolithic integration; gallium nitride; high-k dielectric; silicon CMOS

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We demonstrate industry's first 300 mm GaN transistor technology and 3-D monolithic heterogeneous integration with Si transistors, enabled by 300 mm GaN metal-organic chemical vapor deposition (MOCVD) epitaxy and 300 mm 3-D layer transfer. The 300 mm GaN technology is a high-k dielectric enhancement-mode GaN nMOS transistor technology on Si(111) substrate. It is capable of excellent characteristics and figure-of-merits (FOM) for realizing energy-efficient, compact power-delivery and RF front-end components such as power-amplifiers, low-noise amplifiers, and RF-switches. Our GaN nMOS transistors show e-mode operation with: 1) high I-D,I-max = 1.5 mA/mu m; 2) low R-ON of 610 Omega - mu m (L-G = 50 nm); 3) low I-OFF of 100 pA/mu m (L-G = 180 nm), which are significant improvements over GaN HEMT; 4) excellent RF performance: f(T) = 190 GHz, f(MAX) = 300 GHz, power-added efficiency (PAE) = 56% (L-G = 50 nm) at mmwave frequency 28 GHz, and PAE = 77% at 5 GHz (L-G = 180 nm), significantly better than industry-standardGaAs and Si RF transistors; 5) good RF-switch FOM, RONCOFF = 110 fs; and 6) low noise figure, NFmin = 1.36 dB (f = 28 GHz) and 0.4 dB (f = 5 GHz), all at SoC-compatible voltages. We further demonstrate GaN transistor innovations all integrated on 300 mm Si(111) wafer, including depletion-mode GaN nMOS transistor with high I-D = 1.8 mA/mu m; GaN Schottky gate transistor producing high saturated power of 20 dBm (80 mu m width) with peak PAE = 57% at 28 GHz; low leakage compact cascode and multigate GaN transistors; and GaN Schottky diodes with ultralow C-OFF for electrostatic discharge (ESD) protection. The layer-transferred Si transistors, monolithically stacked on top of the GaN transistors by 300 mm 3-D layer transfer, show high drive current performance: 1.0 mA/mu m (Si nMOS) and 0.5 mA/mu m (Si pMOS). Such a monolithic 3-D Monolithic integration of GaN and Si transistors enables full integration of energy-efficient, truly compact power delivery and RF solutionswith CMOS digital signal processing, logic computation and control, memory, and analog circuitries.

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