Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 55, Issue 12, Pages 3260-3270Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2020.3016656
Keywords
Amplifier noise; analog-to-digital converter (ADC); comparator preamp; input driver; kT/C noise cancellation; reference buffer; sampling noise; successive approximation register (SAR)
Categories
Funding
- NSFC [61904094, 61934009]
- China Postdoctoral Science Foundation [2020M670329]
- Beijing National Research Center for Information Science and Technology
- Beijing Innovation Center for Future Chip
Ask authors/readers for more resources
As any analog-to-digital converter ( ADC) with a front-end sample-and-hold (S/H) circuit, successive approximation register (SAR) ADC suffers from a fundamental signalto-noise ratio (SNR) challenge: its sampling kT/C noise. To satisfy the SNR requirement, the input capacitor size has to be sufficiently large, leading to a great burden for the design of the ADC input driver and reference buffer. This article presents an SAR ADC with a kT/C noise-cancellation technique. It enables the substantial reduction of ADC input capacitor size but without the large kT/C noise penalty. It greatly relaxes the requirement for ADC input driver and reference buffer. Built in 40-nm CMOS, a prototype 13-bit ADC has only 240-fF input capacitance and occupies a small area of 0.005 mm(2). Operating at 40 MS/s, it achieves a 69-dB signal-to-noise-and-distortion ratio (SNDR) across the Nyquist frequency band while consuming 591 mu W of power.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available