Article
Engineering, Electrical & Electronic
Julia Stoettner, Christian Hanzl, Christian Endisch
Summary: This paper investigates the optimization of conventional power electronics in electric vehicles using multilevel inverters (MLIs). The focus is on cascaded MLIs and the crucial design parameter of individual MLI modules. The study compares symmetrical and asymmetrical cascaded MLIs and concludes that symmetrical MLIs generally have higher redundancy of voltage levels, while asymmetrical MLIs can achieve an increase in the number of different levels. By using a special design rule, asymmetrical MLIs can achieve the same output voltage resolution as symmetrical MLIs while keeping the number of modules low. However, the asymmetrical nature of the modules may negatively impact the power balance of the inverter. The paper also discusses the total harmonic distortion and finds that configurations with a high number of voltage levels and symmetrical output voltage patterns achieve the lowest distortion.
ELECTRIC POWER SYSTEMS RESEARCH
(2022)
Article
Engineering, Electrical & Electronic
Malik Muhammad Zaid, Hamza Ahmad, Sadjad Madanzadeh, Jong-Suk Ro
Summary: This paper introduces a novel pd-type multilevel inverter topology that can generate low total harmonic distortion and voltage stress across the switches, while minimizing the number of components. By using cascaded connections, the output voltage levels can be expanded, making it suitable for medium- and high-voltage applications with different numbers of dc links. The use of nearest level control modulation technique enables minimum THD at the output.
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS
(2022)
Article
Computer Science, Information Systems
Satilmis Urgun, Halil Yigit, Seyedali Mirjalili
Summary: Multilevel inverters (MLI) are widely used in high-power applications. The selective harmonic elimination (SHE) method is employed to reduce switching and eliminate desired harmonics. Classical methods have limitations, so metaheuristic algorithms are used to find better solutions. Extensive analysis of 22 metaheuristic algorithms was performed, and the methods SPBO, BMO, GA, GWO, MFO, and SPSA were found to offer the best performance.
Article
Computer Science, Artificial Intelligence
Halil Yigit, Satilmis Urgun, Seyedali Mirjalili
Summary: This study employs various metaheuristic algorithms to find the best optimization framework for identifying switching moments in an 11-level multilevel inverter. Simulation results show that the Moth Flame Optimizer (MFO) outperforms other algorithms in terms of Total Harmonic Distortion (THD) minimization, convergence rate, single iteration time, and robustness.
NEURAL COMPUTING & APPLICATIONS
(2023)
Article
Engineering, Chemical
Mohammad Wasiq, Adil Sarwar, Zeeshan Sarwer, Mohd Tariq, Shafiq Ahmad, Adel M. Al-Shayea, Jahangir Hossain
Summary: The paper presents a reduced switching components step-up multilevel inverter capable of generating 11 levels in the output voltage with reduced number of switching components. The proposed circuit features low voltage stresses, inherent generation of voltage levels for the negative half, and utilizes fundamental frequency switching technique for generating switching signals. Experimental results show a total harmonic distortion of 9.4% for the output voltage, and a comparative study based on different parameters strengthens the claim of the proposed multilevel inverter.
Article
Green & Sustainable Science & Technology
Md Reyaz Hussan, Mohammad Irfan Sarwar, Adil Sarwar, Mohd Tariq, Shafiq Ahmad, Adamali Shah Noor Mohamed, Irfan A. Khan, Mohammad Muktafi Ali Khan
Summary: Multilevel inverters (MLIs) have the capability to produce high-quality output voltage and handle large amounts of power. They have a wide range of applications in industries, particularly in smart grids. This paper presents a seven-level modified H-bridge inverter with a reduced component count and reduced total harmonic distortion (THD).
Article
Computer Science, Information Systems
S. Govind, Anilkumar Chappa, K. Dhananjay Rao, Subhojit Dawn, Taha Selim Ustun
Summary: A new generalized condition is proposed in this paper for the selective harmonic elimination technique to achieve the elimination of harmonic content and improvement of THD in the output voltage, while reducing switching losses.
Article
Engineering, Electrical & Electronic
Anil Kumar Yarlagadda, Vimlesh Verma
Summary: This paper proposes a multilevel DC-link inverter (MLDCLI) with level doubling source (LDS) for photovoltaic application. The proposed topology uses minimal number of switches, DC sources, and capacitors compared to existing topologies.
ELECTRICAL ENGINEERING
(2022)
Article
Engineering, Electrical & Electronic
Salvatore Foti, Tommaso Scimone, Antonio Oteri, Giacomo Scelba, Antonio Testa
Summary: This article proposes a new dual T-type 13-level inverter topology that requires fewer power switches, gate drivers, and diodes compared to traditional multilevel topologies. It also eliminates the need for additional circuits to equalize capacitor voltages and complex modulation strategies, resulting in cost and power loss reduction. Experimental tests confirm that the proposed topology performs well in terms of efficiency and total harmonic distortion.
IEEE TRANSACTIONS ON POWER ELECTRONICS
(2023)
Article
Energy & Fuels
Manita Kumari, Adil Sarwar, Mohd Tariq, Shafiq Ahmad, Adamali Shah Noor Mohamed, Eduardo M. G. Rodrigues
Summary: This paper presents a study on a three-phase multilevel inverter that utilizes switching capacitors and a single DC power supply to produce a nine-stage, three-phase voltage output. The optimal switching angles for Selective Harmonic Elimination (SHE) are determined using a recently proposed meta-heuristic technique called symbiotic organism search (SOS). The converter performance is analyzed in the MATLAB/SIMULINK environment and validated with real-time hardware-in-the-loop (HIL) experiment results.
Article
Engineering, Electrical & Electronic
Dhanamjayulu Chittathuru, Sanjeevikumar Padmanaban, Ramjee Prasad
Summary: A novel asymmetrical cascaded one-twenty-five level multilevel inverter with optimal components is proposed, generating a 125-level output voltage. The inverters show very low harmonics and are stable under dynamic circumstances, meeting IEEE standards for grid-connected and renewable applications.
ELECTRIC POWER COMPONENTS AND SYSTEMS
(2021)
Article
Engineering, Electrical & Electronic
G. Vivek, Meenu D. Nair, Jayanta Biswas, Mukti Barai
Summary: This paper presents a design space exploration method of hybrid SVPWM techniques for three level voltage source inverter (VSI) to reduce total harmonic distortion (THD) and switching loss. Two optimized hybrid SVPWM techniques are proposed and implemented on a low cost PIC microcontroller, showing improved performance in experimental results.
ELECTRICAL ENGINEERING
(2021)
Article
Energy & Fuels
Shoeb Ahmad Khan, Adil Sarwar, Mohd Tariq, Shabana Urooj, Md Alamgir Hossain
Summary: This paper investigates a new nine-level Packed-E-Cell (PEC) multilevel inverter topology for its fault-tolerant capability and improved reliability. The fault-tolerant topology provides additional redundant states in the switching sequence and achieves self-voltage balance in the DC-link capacitors. Simulation results in MATLAB/Simulink and experimental verification are conducted.
Article
Computer Science, Information Systems
Giuseppe Schettino, Antonino Oscar Di Tommaso, Rosario Miceli, Claudio Nevoloso, Gioacchino Scaglione, Fabio Viola
Summary: To prevent leg short-circuits in inverters, dead time must be introduced in leg gate signals. Dead time affects the fundamental harmonic amplitude, voltage harmonic distortion, and efficiency of the inverter by introducing additional voltage drops. This paper analyzes the impact of dead time on the harmonic distortion and efficiency of Cascaded H-Bridges Multilevel Inverters (CHBMIs) and provides a mathematical formulation to determine voltage drop due to dead time effects.
Article
Engineering, Electrical & Electronic
Weiqiang Chen, Ali Bazzi
Summary: This article introduces a model-based voltage quality analysis and optimization method for post-fault reconfigured N-level Neutral Point Clamped (NPC) inverter, aiming to address the significant degradation of voltage quality in post-fault reconfigured multilevel inverters (MLIs) which may impact critical applications. By reviewing existing voltage quality and mathematical analyses of MLIs, a suitable mathematical model for N-level NPC inverter is proposed in order to accurately describe its voltage quality. An optimization method is also introduced based on the accurate mathematical model to alleviate the voltage quality degradation issue in post-fault reconfigured N-level NPC inverter.
IEEE TRANSACTIONS ON POWER ELECTRONICS
(2021)
