Optimized buffer insertion for efficient interconnects designs

This typescript focuses on unraveling the functional performance deterioration issues related to conventional Cu on-chip nanointerconnecting wires; mainly occurred due to the shrinking of device dimensions. Buffer insertion methodology proves to be an effective approach for designing high-speed interconnect network but at the cost of power consumption. Moreover, ramification of too many buffers as repeaters leads to area overhead. Hence an optimized number must be judicially decided. Proposed circuits for buffers are modeled using variable diameter and multi V- t design techniques to balance delay as well as average power consumption. Interconnects designed with conventional Cu interconnect technology are compared with state of art CNT technology at different lengths. Proposed and Existing Buffer circuit architectures are modeled with both CNT and MOS technology to carry out the comparative simulation analysis using varied combination of CNTFET buffer-CNT interconnect and CMOSFET buffer-Cu interconnect. Benchmarking with conventional buffer circuits, simulated results illustrates that ProposedBuffer1 saves dynamic power by 89.96%, leakage power by 89%, and offers delay mitigation by 77.5%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 97.53%, but causes delay penalty. All the HSPICE simulations are carried out using Stanford SPICE model for CNT and BSIM4 PTM for MOS at 32 nm.