Power and performance analysis of 3D network-on-chip architectures

Published 2020 View Full Article

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Title
Power and performance analysis of 3D network-on-chip architectures
Authors
Keywords
Network-on-chip (NoC) 3D NoC Topologies, Through-silicon via (TSV), Design space exploration, performance analysis, Energy Delay Product
Journal
COMPUTERS & ELECTRICAL ENGINEERING
Volume 83, Issue -, Pages 106592
Publisher
Elsevier BV
Online
2020-03-11
DOI
10.1016/j.compeleceng.2020.106592

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