Design and Optimization of VCSELs for up to 40-Gb/s Error-Free Transmission Through Impurity-Induced Disordering

Title
Design and Optimization of VCSELs for up to 40-Gb/s Error-Free Transmission Through Impurity-Induced Disordering
Authors
Keywords
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Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 67, Issue 3, Pages 1041-1046
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2020-02-06
DOI
10.1109/ted.2020.2966364

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