Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 67, Issue 1, Pages 1-11Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2019.2944396
Keywords
Jitter; jitter suppression; clock; S/H; sampling; delta-sigma; high speed; ADC
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Funding
- DARPA CLASIC Program
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In this paper, we discuss the limitations of the existing clock jitter reduction techniques, and introduce Delta Sigma sampling, which can reduce the jitter-induced sampling error significantly. We investigate various feedback configurations, and show that NRZ and RZ feedback techniques both improve the jitter shaping properties of the Delta Sigma sampler. However, in order to benefit from the superior jitter shaping, a constant feedback pulsewidth is required. We propose a new clocking scheme, called correlated clocking to address the feedback pulsewidth variations. This technique utilizes the correlation between the rising and falling edges of the on-chip clocks to eliminate the feedback pulsewidth jitter. We show that a 1(st) -order Delta Sigma sampler with correlated RZ feedback can achieve the same SJNR as a Delta Sigma sampler with switched-capacitor feedback. We then expand our analysis to 2(nd) - and higher-order modulators, and show that contrary to common belief, even with constant-pulsewidth feedback, higher-order modulators are limited by the feedback pulse jitter. We conclude that the maximum benefit of a Delta Sigma sampler with a conventional single-loop architecture is independent of the loop order, feedback mechanism, and the oversampling ratio, and it reaches 4.77 dB for OSR >= 5.
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