Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 55, Issue 3, Pages 680-692Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2019.2946215
Keywords
Capacitors; Switches; Reservoirs; Prototypes; System-on-chip; Analog-digital conversion; CMOS process; Analog-to-digital converter (ADC); high speed; reference ripple; reference ripple cancellation; successive approximation register
Categories
Funding
- NSF [1254459, 1509767, 1527320]
- National Natural Science Foundation of China [61625403, 61874174, 61934009]
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This article presents a reference ripple cancellation technique for high-speed successive approximation register analog-to-digital converters (SAR ADCs) to address the reference voltage settling issue. Unlike prior techniques that aim to minimize the reference ripple, this article proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. To verify the proposed technique, a prototype 10-bit 120-MS/s SAR ADC is fabricated in a 40-nm CMOS process. The proposed ripple cancellation technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL)/differential non-linearity (DNL) by ten times. Overall, the ADC achieves an SNDR of 55 dB with only 3-pF reference decoupling capacitor.
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