Balanced sampling switch for high linearity and a wide temperature range in low power SAR ADCs

This Letter proposes a balanced sampling switch technique for achieving high linearity and a wide temperature range. The proposed technique reduces the V-DS of the NMOS sampling switch for reducing the leakage current through the switch during the hold mode. This operation is implemented by a mini capacitive digital-to-analogue converter (C-DAC) that mimics the main C-DAC used for main SAR conversion. The proposed sampling switch is applied to a 10-bit, 0.5 V SAR ADC with 5 Msample/s and verified by comprehensive simulation. Compared to the conventional sampling switch without the mini C-DAC, the proposed switch improves SFDR and SNDR by 27.52 dBc and 11.8 dB, respectively, at the FF corner and 120 degrees C.