4.5 Article

Tuning of electrical hysteresis in PMMA/GOs/PMMA multi-stacked devices

Journal

MATERIALS RESEARCH EXPRESS
Volume 6, Issue 8, Pages -

Publisher

IOP PUBLISHING LTD
DOI: 10.1088/2053-1591/ab26d3

Keywords

multi-stacking; tunable electrical hysteresis; charge trapping; polymer; graphene oxides; spin coating

Funding

  1. TEQIP-III under National Project Implementation Unit (NPIU), NIT Silchar

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Graphene Oxide (GOs) has gained a lot of attention because of its incredible character as chargetrapping material in the memory devices. In the present study, we report the electrical hysteresis in multi-stacked (PMMA/GOs/PMMA) devices sandwiched between ITO and Al electrodes. A thin layer of GOs was inserted between the PMMA layers and the thickness of the polymer layers were varied to study the electrical properties of the multi-stacked devices. Hummer's method was used for the synthesis of GOs and was characterized through different optical techniques such as UV-Visible absorption, Photoluminescence (PL), Raman and Fourier Transform Infrared (FTIR) spectroscopy. Structural and morphological analysis were performed through x-ray diffraction (XRD), Transmission Electron microscopy (TEM) and Scanning Electron Microscopy (SEM). The room temperature J-V characteristics of the multi-stacked devices were studied and the hysteresis area was found to be increasing with the increase in sweep voltage and decrease in film thickness of PMMA, respectively. The hysteresis is repeatable and highly stable for the multi-stacked devices as compared to ITO/ PMMA/A1 devices, spin-coated at same RPM and under identical voltage sweeps. On the basis of J-V results, a suitable energy-band diagram is proposed to explain the carrier transport through the multistacked devices.

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