Article
Engineering, Electrical & Electronic
Sepehr Tabrizchi, Fazel Sharifi, Parisa Dehghani
Summary: The full adder cell is a crucial module in arithmetic and processing systems, and utilizing carbon nanotube field effect transistors in the design can significantly reduce energy consumption and enhance robustness.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
(2021)
Article
Chemistry, Analytical
Ramzi A. Jaber, Ali M. Haidar, Abdallah Kassem, Furqan Zahoor
Summary: The paper presents two new designs of Ternary Full Adders (TFA) using Carbon Nanotube Field-Effect Transistors (CNFET), namely TFA1 with 59 CNFETs and TFA2 with 55 CNFETs. These designs utilize unary operator gates with two voltage supplies (V-dd and V-dd/2) to reduce transistor count and energy consumption. Two 4-trit Ripple Carry Adders (RCA) based on TFA1 and TFA2 are also proposed. Simulation results using HSPICE and 32 nm CNFET show significant improvements in energy consumption (PDP) and Energy Delay Product (EDP), with reductions of over 41% and 64%, respectively, compared to the best recent works in the literature.
Article
Engineering, Electrical & Electronic
Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri
Summary: The paper proposes a dynamic ternary full adder using CNFETs, which has lower power consumption and greater robustness. Through simulation verification, the performance of this method is shown to be superior to previous ternary adders under different conditions.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
(2021)
Article
Mathematics
Seyed Hossein Shahrokhi, Mehdi Hosseinzadeh, Midia Reshadi, Saeid Gorgin
Summary: This paper presents a new and high-performance inaccurate Full Adder Cell utilizing the Carbon Nanotube Field Effect Transistor (CNFET) technology. Comprehensive simulations are performed to justify the performance of the design at the transistor and application levels. The simulations using HSPICE confirm the significant improvement in circuit delay, power-delay product (PDP) and energy-delay product (EDP) compared to competitor designs. Moreover, software simulations using MATLAB tool confirm the suitable quality of the final images in the image blending application.
Article
Computer Science, Hardware & Architecture
Mohammad-Ali Asadi, Mohammad Mosleh, Majid Haghparast
Summary: Integrated circuits face challenges of heat and area occupation, with strategies like reversible circuits and multiple-valued logic proving effective. Efficient use of multiple-valued logic capabilities is key to reducing complexity and delays in computational circuits. The proposed reversible circuits show superiority in quantum cost despite similarities in other criteria with previous designs.
JOURNAL OF SUPERCOMPUTING
(2021)
Article
Engineering, Electrical & Electronic
Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan
Summary: This paper presents a carbon nanotube FET-based ultra-low-power dualVDD ternary half adder circuit, which significantly reduces power dissipation compared to conventional designs and has lower delays. The proposed design consumes significantly less power and exhibits lower delays compared to other CNFET and CMOS ternary half adder designs.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
(2021)
Article
Engineering, Electrical & Electronic
Seied Ali Hosseini, Esmail Roosta
Summary: In this paper, novel circuits are designed based on the multi-threshold voltage of CNFET to produce logic '1' by charging or discharging a load capacitor using a unique structure of diode-connected transistors. By utilizing a single-supply voltage, direct current is eliminated and static power consumption is significantly reduced. Simulation results demonstrate considerably low power consumption with the same delay, offering a lower PDP compared to other single-supply designs with the same noise margin.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
(2021)
Article
Computer Science, Hardware & Architecture
Ali Ghorbani, Mehdi Dolatshahi, S. Mohammadali Zanjani, Behrang Barekatain
Summary: This paper proposes a new low-power full-adder circuit based on the proper combination of dynamic logic style and GDI low-power technique in CNFET technology. The proposed circuit achieves full-swing, full-adder cell and shows significant improvement in major circuit performances through simulations.
INTEGRATION-THE VLSI JOURNAL
(2022)
Article
Engineering, Electrical & Electronic
Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri
Summary: This paper introduces a ternary half adder and a 1-trit multiplier designed using carbon nanotube transistors, which have advantages over MOSFETs and provide lower power consumption, delay, and transistor count. The proposed circuits exhibit robust performance over a wide range of operating conditions, with improved efficiency compared to previous designs.
MICROELECTRONICS JOURNAL
(2021)
Article
Engineering, Electrical & Electronic
Zahra Zareei, Mehdi Bagherizadeh, MohammadHossein Shafiabadi, Yavar Safaei Mehrabani
Summary: Two novel approximate Full Adder cells with capacitive threshold logic using carbon nanotube field-effect transistor technology are presented in this paper. Extensive simulations are carried out to investigate the efficiency of the proposed cells at both application and transistor levels. The results show the superiority of the proposed cells compared to others, considering a compromise between application and hardware-level metrics.
MICROELECTRONICS JOURNAL
(2021)
Article
Chemistry, Analytical
Avireni Bhargav, Phat Huynh
Summary: In this study, 10T and 13T approximate adder designs using CNFET technology were proposed, showcasing excellent performance in terms of energy efficiency and accuracy compared to existing circuit designs.
Article
Engineering, Electrical & Electronic
Seyed Hossein Shahrokhi, Mehdi Hosseinzadeh, Midia Reshadi, Saeid Gorgin
Summary: A novel inexact Full Adder cell based on carbon nanotube field-effect transistor technology is proposed and investigated through simulations under different conditions, with application to an image blending system. The results demonstrate superior performance of the proposed cell in various metrics at both transistor and application levels.
INTERNATIONAL JOURNAL OF ELECTRONICS
(2022)
Article
Physics, Multidisciplinary
Saeid Seyedi, Nima Jafari Navimipour
Summary: QCA technology offers higher performance, smaller size, and lower power consumption compared to traditional CMOS technology. Circuits designed using QCA technology have lower delay and require fewer cells.
INTERNATIONAL JOURNAL OF THEORETICAL PHYSICS
(2021)
Article
Computer Science, Hardware & Architecture
Yavar Safaei Mehrabani, Samaneh Goldani Gigasari, Mohammad Mirzaei, Hamidreza Uoosefian
Summary: This paper presents a novel and efficient inexact Full Adder cell utilizing carbon nanotube field-effect transistor (CNFET) technology and two logic styles - conventional CMOS (C-COMS) and pass transistor logic (PTL). Extensive simulations at transistor level and application level demonstrate higher performance in terms of power-delay-area product (PDAP compared to latest designs. Application level simulations using MATLAB show the quality of output images in terms of peak signal-to-noise ratio (PSNR) and structural similarity (SSIM). The proposed circuit shows significant improvement in power-delay-area-PSNR product (PDAPP) and power-delay-area-SSIM product (PDASP) compared to its counterparts.
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS
(2022)
Article
Nanoscience & Nanotechnology
Sepehr Tabrizchi, Fazel Sharifi, Abdel-Hameed Badawy
Summary: This paper introduces a novel method for designing ternary logic circuits based on carbon nanotube field-effect transistors (CNFETs). The proposed circuits have been simulated and shown to operate correctly under different process, voltage, and temperature variations. Additionally, the two-digit adder/subtractor and power-efficient ternary logic ALU using the proposed gates exhibit significantly lower power consumption and power-delay product compared to previous designs.
INTERNATIONAL JOURNAL OF NANOSCIENCE
(2022)
Article
Optics
Hojjat Sharifi, Fazel Sharifi
Summary: A general method for designing all optical MVL decoders and encoders is proposed in this paper. The structures presented use threshold detectors based on nonlinear photonic crystal ring resonators, where the nonlinear optical Kerr effect is employed to control the transmission amount by input signal power. The proposed structures achieve small dimensions and propagation delay, and exhibit good contrast ratios between logic levels.
Article
Nanoscience & Nanotechnology
Sepehr Tabrizchi, Fazel Sharifi, Abdel-Hameed Badawy
Summary: This paper introduces a novel method for designing ternary logic circuits based on carbon nanotube field-effect transistors (CNFETs). The proposed circuits have been simulated and shown to operate correctly under different process, voltage, and temperature variations. Additionally, the two-digit adder/subtractor and power-efficient ternary logic ALU using the proposed gates exhibit significantly lower power consumption and power-delay product compared to previous designs.
INTERNATIONAL JOURNAL OF NANOSCIENCE
(2022)
Article
Computer Science, Hardware & Architecture
Hossein Momeni, Amir Ghazizadeh, Fazel Sharifi
Summary: This study proposes two new designs of MVL APUFs using CNTFETs, which enhance APUF security by increasing the size of challenge-response pairs. The experimental results show that the proposed designs have high randomness and reliability under different temperatures and voltages.
COMPUTERS & ELECTRICAL ENGINEERING
(2022)
Article
Engineering, Electrical & Electronic
Sepehr Tabrizchi, Ali Nezhadi, Shaahin Angizi, Arman Roohi
Summary: This paper introduces an architecture called AppCiP that efficiently enables artificial intelligence on resource-limited sensing devices. AppCiP features instant and reconfigurable RGB to grayscale conversion, highly parallel analog convolution-in-pixel, and low-precision quinary weight neural networks. The circuit-to-application co-simulation results show that AppCiP achieves significantly higher power consumption efficiency compared to existing designs, with a frame rate of 3000 and an efficiency of 4.12 TOp/s/W. The performance accuracy of AppCiP on different datasets is evaluated and compared with state-of-the-art designs, showing the best results among other processing in/near pixel architectures with less than 1% degradation in accuracy.
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS
(2023)
Article
Engineering, Electrical & Electronic
Sepehr Tabrizchi, Shaahin Angizi, Arman Roohi
Summary: This paper proposes an efficient new architecture called Ocelli, which introduces technologies such as compute add-ons and non-volatile magnetic RAM to enable efficient computation of convolutional neural networks on embedded edge devices with limited energy budgets and hardware. The proposed architecture achieves improved power efficiency and accuracy.
JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS
(2022)
Article
Engineering, Electrical & Electronic
Mehrdad Morsali, Sepehr Tabrizchi, Andrew Marshall, Arman Roohi, Durga Misra, Shaahin Angizi
Summary: This article presents a near-sensor processing (NSP) platform utilizing magneto-electric FETs (MEFETs) that enables low-cost event detection for edge vision sensors by eliminating power-hungry ADCs. Additionally, an efficient background comparison method with adjustable precision is introduced, providing a tradeoff between output quality and efficiency. Device-to-architecture evaluations show that the proposed hardware-software codesign reduces energy consumption and execution time by approximately 15x and 2.4x compared to the SOT-MRAM counterpart using the same method.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Proceedings Paper
Computer Science, Artificial Intelligence
Sepehr Tabrizchi, Mehrdad Morsali, Shaahin Angizi, Arman Roohi
Summary: This paper proposes an effective background subtraction approach, NeSe, for tiny energy-harvested sensors using non-volatile memory (NVM). The precision of event detection can be adjusted at runtime by changing the precision depending on the application's needs. By implementing background subtraction on the sensor nodes and using NVM for background storage, the design reduces data movement overhead and ensures intermittent resiliency.
2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS
(2023)
Proceedings Paper
Computer Science, Artificial Intelligence
Sepehr Tabrizchi, Rebati Gaire, Shaahin Angizi, Arman Roohi
Summary: In this paper, we propose an ultra-low-power in-sensor architecture called SenTer, which enables low-precision ternary multi-layer perceptron networks in detection and classification modes. SenTer supports two activation functions and significantly reduces overhead by performing computations in the analog domain and using only one ADC. Our simulation results show acceptable accuracy compared to full precision models on various datasets.
PROCEEDINGS OF THE GREAT LAKES SYMPOSIUM ON VLSI 2023, GLSVLSI 2023
(2023)
Proceedings Paper
Automation & Control Systems
Ranyang Zhou, Sepehr Tabrizchi, Mehrdad Morsali, Arman Roohi, Shaahin Angizi
Summary: In this work, we propose a Parallel Processing-In-DRAM architecture named P-PIM that leverages the high density of DRAM for fast and flexible computation. P-PIM enables bulk bit-wise in-DRAM logic by elevating the analog operation of the memory sub-array based on a novel dual-row activation mechanism. It also provides a complete and inexpensive in-DRAM RowHammer self-tracking and mitigation technique for memory unit protection. Experimental results show that P-PIM achieves significantly higher energy efficiency compared to charge-sharing-based designs, and offers substantial energy-saving in RH protection compared to SRAM/CAM-based and DRAM-based frameworks.
2023 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE
(2023)
Proceedings Paper
Computer Science, Hardware & Architecture
Mehrdad Morsali, Ranyang Zhou, Sepehr Tabrizchi, Arman Roohi, Shaahin Angizi
Summary: In this work, a digital Computing-in-Memory (CiM) platform called XOR-CiM is developed by leveraging the uni-polar switching behavior of Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM). XOR-CiM converts MRAM sub-arrays to parallel computational cores with high bandwidth, reducing energy consumption and accelerating inference for X(N)OR-intensive Binary Neural Networks (BNNs). Compared to recent MRAM-based CiM platforms, XOR-CiM achieves similar inference accuracy but shows approximately 4.5x and 1.8x higher energy-efficiency and speed-up.
2023 24TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, ISQED
(2023)
Proceedings Paper
Engineering, Electrical & Electronic
Sepehr Tabrizchi, Shaahin Angizi, Arman Roohi
Summary: This work proposes a new generic Single-cycle Compute-in-Memory (CiM) Accelerator named SCiMA for matrix computation. By utilizing specifically designed single-cycle in-memory bulk bitwise functions, SCiMA can accelerate a wide variety of graph and matrix multiplication tasks. Experimental results show that SCiMA can reduce energy consumption by 70.43% compared with the most recent CiM designs implemented with the same memory technology and achieve up to 2.5x speedup compared with current CiM platforms.
2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22)
(2022)
Proceedings Paper
Computer Science, Hardware & Architecture
Sepehr Tabrizchi, Shaahin Angizi, Arman Roohi
Summary: This paper proposes TizBin, a low-power processing in-sensor scheme with event and object detection capabilities, to enable data-intensive neural network tasks. TizBin offers unique features such as analog convolutions and non-volatile magnetic RAMs, reducing power consumption and achieving high efficiency.
2022 IEEE 40TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2022)
(2022)
Article
Computer Science, Hardware & Architecture
Ranyang Zhou, Sepehr Tabrizchi, Arman Roohi, Shaahin Angizi
Summary: In this research, we propose LT-PIM, a Lookup Table-based Processing-In-Memory architecture that leverages the high density of DRAM for parallel and flexible computation. LT-PIM supports lookup table queries for complex arithmetic operations and enables bulk bit-wise in-memory logic. It also achieves a complete and inexpensive in-DRAM RowHammer self-tracking approach. Experimental results show that LT-PIM achieves significantly higher energy efficiency and energy-saving compared to other designs, making it a promising solution for memory processing.
IEEE COMPUTER ARCHITECTURE LETTERS
(2022)
Proceedings Paper
Engineering, Electrical & Electronic
Sepehr Tabrizchi, Shaahin Angizi, Arman Roohi
Summary: This paper presents a novel ternary Static Random Access Memory (T-SRAM) cell that eliminates the need to store the voltage level of the intermediate ternary state, thus reducing leakage power and increasing robustness.
2022 IEEE 65TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS 2022)
(2022)
Article
Computer Science, Hardware & Architecture
Jia Ke, Ying Wang, Mingyue Fan, Xiaojun Chen, Wenlong Zhang, Jianping Gou
Summary: This study integrates the emotional correlation analysis model and Self-organizing Map (SOM) to construct fine-grained user emotion vector based on review text and perform visual cluster analysis, which helps platform merchants quickly mine user clustering and characteristics.
COMPUTERS & ELECTRICAL ENGINEERING
(2024)
Article
Computer Science, Hardware & Architecture
Shi Qiu, Huping Ye, Xiaohan Liao, Benyue Zhang, Miao Zhang, Zimu Zeng
Summary: This paper proposes a multilevel-based algorithm for hyperspectral image interpretation, which achieves semantic segmentation through multidimensional information fusion, and introduces a context interpretation module to improve detection performance.
COMPUTERS & ELECTRICAL ENGINEERING
(2024)
Article
Computer Science, Hardware & Architecture
Jianteng Xu, Qingguo Bai, Zhiwen Li, Lili Zhao
Summary: This study constructs two optimization models for the omnichannel closed-loop supply chain by leveraging the combined power of leader-follower game and mean-variance theories. The focus is on analyzing the performance of manufacturers who distribute products through physical stores. The results show that the risk-averse attitude of the physical store has a positive impact on the overall system profitability, but if the introduced physical store belongs to another firm, total profit experiences a decline.
COMPUTERS & ELECTRICAL ENGINEERING
(2024)
Article
Computer Science, Hardware & Architecture
Jiahao Xiong, Weihua Ou, Zhonghua Liu, Jianping Gou, Wenjun Xiao, Haitao Liu
Summary: This paper proposes a novel remote photoplethysmography framework, named GraphPhys, which utilizes graph neural network to extract physiological signals and introduces Average Relative GraphConv for the task of remote physiological signal measurement. Experimental results show that the methods based on GraphPhys significantly outperform the original methods.
COMPUTERS & ELECTRICAL ENGINEERING
(2024)
Article
Computer Science, Hardware & Architecture
Zhiyao Tong, Yiyi Hu, Chi Jiang, Yin Zhang
Summary: The rise of illicit activities involving blockchain digital currencies has become a growing concern. In order to prevent illegal activities, this study combines financial risk control with machine learning to identify and predict the risks of users with poor credit. Experimental results demonstrate high performance in user financial credit analysis.
COMPUTERS & ELECTRICAL ENGINEERING
(2024)
