Journal
ELECTRONICS
Volume 8, Issue 5, Pages -Publisher
MDPI
DOI: 10.3390/electronics8050572
Keywords
three-stage CMOS amplifiers; cascode miller compensation; local Q-factor control; pole-zero cancellation; wide drivability range
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Funding
- National Natural Science Foundation of China [61874143]
- Shenzhen Research and Development Funds for Science and Technology [JCYJ20180508152019687]
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This paper presents a new frequency compensation approach for three-stage amplifiers driving a pF-to-nF capacitive load. Thanks to the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively, and the physical size of the compensation capacitors is also reduced. A local Q-factor control (LQC) loop is introduced to alter the Q-factor adaptively when loading capacitance C-L varies significantly. This LQC loop decides how much damping current should be injected into the corresponding parasitic node to control the Q-factor of the complex-pole pair, which affects the frequency peak at the gain plot and the settling time of the proposed amplifier in the closed-loop step response. Additionally, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Simulated in 0.13-mu m CMOS technology, the amplifier is verified to handle a 4-pF-to-1.5-nF (375x drivability) capacitive load with at least 0.88-MHz gain-bandwidth (GBW) product and 42.3 degrees phase margin (PM), while consuming 24.0-mu W quiescent power at 1.0-V nominal supply voltage.
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