An Analytical Model for the Effective Drive Current in CMOS Circuits

Inverter delay is often evaluated as CVdd/I-eff, where C is the load capacitance, V-dd is the supply voltage, and I-eff is the effective drive current derived by approximating the inverter switching trajectory with a linear model. The I-eff model utilizes high and low drain currents conventionally measured in wafer acceptance tests and does not require extraction of any parameters. Ease of use combined with reasonable accuracy (similar to 15%) is the main reason for wide application of CVdd/I-eff delay metrics. However, CVdd/I-eff expression produces large errors when applied to another two important basic circuits: nand and nor. This is because nand and nor circuits contain transistor series connections not accounted for in the inverter model. In this paper, an analytical solution for the transistor series connection influence on the discharge/charge operation in nand/nor circuits is provided. The model for nand/nor effective drive current (denoted as I-stack) developed in this paper maintains simplicity of the original Ieff expression. It requires only one additional measurement of the linear current. Model accuracy was assessed by comparing to extensive SPICE delay simulations of nand and nor circuits designed using state-of-the-art MOS technologies. Comparison results show that CVdd/I-stack equation provides similar to 15% accuracy for nand/nor circuits in line with CVdd/I-eff accuracy for inverter. In an era of emphasis on low-power design, the developed model presents convenient means of exploring design space when optimizing circuit supply voltage for low-power operation.