Journal
MICROELECTRONICS JOURNAL
Volume 82, Issue -, Pages 29-35Publisher
ELSEVIER SCI LTD
DOI: 10.1016/j.mejo.2018.10.011
Keywords
Energy-efficient; Switching algorithm; SAR ADC; Capacitor array; Comparator
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This paper configures a successive approximation register (SAR) analog-to-digital converter (ADC) based on a new switching algorithm with efficient energy consumption. The proposed switching algorithm applies the same reference voltage to the bottom plates of all capacitors in each capacitor array to drain no energy through capacitors. In addition to a 100% energy saving in the switched-capacitor digital-to-analog converter (DAC) block, configuration of an N-bit SAR ADC shows a 50% capacitor area reduction in comparison with the conventional SAR ADC.
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