Designing efficient accelerator of depthwise separable convolutional neural network on FPGA

Authors

Keywords

Convolutional neural network, Depthwise separable convolution, Hardware accelerator, FPGA, Edge computing

Journal

Volume -, Issue -, Pages -

Publisher

Elsevier BV

Online

2018-12-29

DOI

10.1016/j.sysarc.2018.12.008

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