An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With $0.175~\mu$ W/Channel in 65-nm CMOS

Published 2018 View Full Article

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Title
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With $0.175~\mu$ W/Channel in 65-nm CMOS
Authors
Keywords
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Journal
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume 27, Issue 1, Pages 126-137
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2018-11-06
DOI
10.1109/tvlsi.2018.2875934

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