4.4 Article

III-V Heterostructure Nanowire Tunnel FETs

Journal

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
Volume 3, Issue 3, Pages 96-102

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JEDS.2015.2388811

Keywords

Tunnel field effect transistors (TFET); InAs; GaSb; III-V; broken gap

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In this paper, InAs/GaSb nanowire tunnel field-effect transistors (TFETs) are studied theoretically and experimentally. A 2-band 1-D analytic tunneling model is used to calculate the on-and off-current levels of nanowire TFETs with staggered source/channel band alignment. Experimental results from lateral InAs/GaSb are shown, as well as first results on integration of vertical InAs/GaSb nanowire TFETs on Si substrates.

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