Low-cost dedicated hardware IP modules for background subtraction in embedded vision systems

This paper presents the design and implementation of dedicated hardware IP modules for background subtraction, which are suitable to be implemented in embedded vision systems and are efficient in terms of performance, resource consumption, and operational speed. To achieve this goal, a comprehensive experimental study of different algorithms has been carried out by evaluating a wide range of quality parameters. From the results of this analysis, five candidate algorithms were selected and implemented using a model-based design methodology supported by Matlab and Xilinx FPGA tools. Using only the internal block memory available in the FPGA, they provide adequate solutions for processing low-resolution images with CIF and QCIF formats.