Journal
IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS
Volume 26, Issue 10, Pages 2596-2601Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNNLS.2015.2388633
Keywords
Floating gate (FG); learning; neuromorphic; neuroscience; spike-timing-dependent plasticity (STDP); synapse; very large scale integration (VLSI)
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Funding
- Ministry of Education, Singapore [ARC 8/13, RG 21/10]
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This brief describes the neuromorphic very large scale integration implementation of a synapse utilizing a single floating-gate (FG) transistor that can be used to store a weight in a nonvolatile manner and demonstrate biological learning rules such as spike-timing-dependent plasticity (STDP). The experimental STDP plot (change in weight against Delta t = t(post) - t(pre)) of a traditional FG synapse from previous studies shows a depression instead of potentiation at some range of positive values of Delta t-we call this non-STDP behavior. In this brief, we first analyze theoretically the reason for this anomaly and then present a simple solution based on changing control gate waveforms of the FG device to make the weight change conform closely to biological observations over a wide range of parameters. The experimental results from an FG synapse fabricated in AMS 0.35-mu m CMOS process design are also presented to justify the claim. Finally, we present the simulation results of a circuit designed to create the modified gate voltage waveform.
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