A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems

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Title
A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems
Authors
Keywords
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Journal
IEEE Computer Architecture Letters
Volume 14, Issue 2, Pages 107-110
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2014-09-30
DOI
10.1109/lca.2014.2360686

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