Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process

Published 2014 View Full Article

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Title
Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process
Authors
Keywords
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Journal
PLoS One
Volume 9, Issue 10, Pages e108634
Publisher
Public Library of Science (PLoS)
Online
2014-10-10
DOI
10.1371/journal.pone.0108634
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