Journal
MICROELECTRONICS JOURNAL
Volume 44, Issue 4, Pages 332-338Publisher
ELSEVIER SCI LTD
DOI: 10.1016/j.mejo.2013.02.012
Keywords
Single-electron tunneling; Shift-register; Logic gate; Room temperature; Stability
Funding
- PQ/CNPq
- CAPES
- INCT/NAMITEC
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This work presents a 4-bit shift-register designed with single-electron tunneling devices. Firstly, a single-electron D flip-flop based on NAND gates was designed and simulated. Based on D flip-flops, the shift-register architecture was also designed and successfully simulated at room temperature. Some considerations about noise margin were made. Moreover, stability analyses for the SET NAND, SET D flip-flop and SET shift-register were carried out. (C) 2013 Elsevier Ltd. All rights reserved.
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