4.2 Article

Effective Cu Filling Method to TSV for 3-dimensional Si Chip Stacking

Journal

KOREAN JOURNAL OF METALS AND MATERIALS
Volume 50, Issue 2, Pages 152-158

Publisher

KOREAN INST METALS MATERIALS
DOI: 10.3365/KJMM.2012.50.2.152

Keywords

electronic materials; plating; defects; scanning electron microscopy (SEM); bottom-up ratio

Ask authors/readers for more resources

The effect of current waveform on Cu filling into TSV (through-silicon via) and the bottom-up ratio of Cu were investigated for three dimensional (3D) Si chip stacking. The TSV was prepared on an Si wafer by DRIE (deep reactive ion etching); and its diameter and depth were 30 and 60 mu m, respectively. SiO2, Ti and Au layers were coated as functional layers on the via wall. The current waveform was varied like a pulse, PPR (periodic pulse reverse) and 3-step PPR. As experimental results, the bottom-up ratio by the pulsed current decreased with increasing current density, and showed a value of 0.38 on average. The bottom-up ratio by the PPR current showed a value of 1.4 at a current density of -5.85 mA/cm(2), and a value of 0.91 on average. The bottom-up ratio by the 3-step PPR current increased from 1.73 to 5.88 with time. The Cu filling by the 3-step PPR demonstrated a typical bottom-up filling, and gave a sound filling in a short time.

Authors

I am an author on this paper
Click your name to claim this paper and add it to your profile.

Reviews

Primary Rating

4.2
Not enough ratings

Secondary Ratings

Novelty
-
Significance
-
Scientific rigor
-
Rate this paper

Recommended

No Data Available
No Data Available