All-copper chip-to-substrate interconnects - Part II. Modeling and design

A fabrication technique involving electro- and electroless copper deposition was used to produce all-copper chip-to-substrate interconnects. This process electrolessly joins copper pillars, followed by annealing at 180 degrees C. The process is tolerant to in-plane and through-plane misalignment and height variations. The mechanical compliance and electrical performance of copper-pillar chip-to-substrate interconnects is modeled in this paper. The elastic, thermomechanical behavior and electrical performance of the chip-to-substrate interconnects are related to the geometric parameters of the pillars (pitch, diameter, and aspect ratio) and physical properties of the interconnects (yield stress, coefficient of thermal expansion, Young's modulus, Poisson's ratio, and electrical conductivity). The optimum pillar design is a trade-off between the mechanical compliance of the copper pillars and parasitic electrical effects. Copper pillars with a diameter of 48-100 mu m and height of 508-657 mu m are mechanically compliant and have parasitic inductance and capacitance less than 300 pH and 8.8 fF, respectively. A polymer collar improves the design space to 38-100 mu m diameter and height from 441 to 617 mu m. (c) 2008 The Electrochemical Society.