Article
Computer Science, Hardware & Architecture
Byoungchan Oh, Nilmini Abeyratne, Nam Sung Kim, Jeongseob Ahn, Ronald G. Dreslinski, Trevor Mudge
Summary: Spin torque magnetic random access memory (STT-MRAM) is considered as an ideal replacement for DRAM-based main memory due to its higher energy efficiency and similar latency. However, simply replacing DRAM with STT-MRAM without optimizations can severely limit its performance. To address these challenges, we propose SMART, a STT-MRAM architecture that supports smart activation and sensing. SMART achieves benefits such as larger pages, fewer sense amplifiers, lower activation power, higher bank-level parallelism, shorter latency, fewer address pins, and more efficient repairing of defective columns compared to conventional STT-MRAM.
IEEE TRANSACTIONS ON COMPUTERS
(2023)
Article
Engineering, Electrical & Electronic
Ariana Musello, Esteban Garzon, Marco Lanuzza, Luis Miguel Procel, Ramiro Taco
Summary: This brief presents a energy-efficient and high-performance XNOR-bitcount architecture using computing-in-memory (CiM) and spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Hardware and algorithmic optimizations are proposed and benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that the hardware optimization reduces the storage requirement for each XNOR-bitcount operation by 50%, while the algorithmic optimization improves execution time and energy consumption by about 30% and 26%, respectively, for single and sequential 9-bit XNOR-bitcount operations. A case study on shape analysis using bit-quads is demonstrated.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2023)
Article
Engineering, Electrical & Electronic
An Yang, Zhilin Jiang, Zheng Huang, Zitong Zhang, Yanfeng Jiang
Summary: A double-ended superposition anti-noise write termination scheme is proposed in this paper to boost sensing margin and improve stability and read performance.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Article
Multidisciplinary Sciences
Carlos Escuin, Pablo Ibanez, Denis Navarro, Teresa Monreal, Jose M. Llaberia, Victor Vinals
Summary: This paper presents a novel LLC organization and a forecasting method for NV-LLC lifetime. The method combines detailed simulation and prediction to analyze the impact of different cache control policies and mechanisms on the temporal evolution of NV-LLC. A new LLC design, L2C2, is also introduced, which combines fault tolerance, compression, and internal write wear leveling to increase the lifetime of NV-LLC.
Article
Computer Science, Hardware & Architecture
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
Summary: This article introduces Spin-Transfer Torque Magnetic RAM (STT-MRAM) as a promising replacement for SRAM in on-chip cache memories and proposes a low-cost scheme called 3RSeT to reduce the occurrence of read disturbance errors in STT-MRAM caches. The evaluations show that 3RSeT significantly reduces the read disturbance rate in the tag array, improves the Mean Time To Failure (MTTF), and reduces energy consumption.
IEEE TRANSACTIONS ON COMPUTERS
(2022)
Article
Computer Science, Hardware & Architecture
Kazi Asifuzzaman, Rommel Sanchez Verdejo, Petar Radojkovi
Summary: There is uncertainty about the future scalability of DRAM and its ability to meet the needs of next-generation systems. Therefore, researchers have been investing significant effort into the development of novel memory technologies. Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the potential candidates for next-generation memory, offering comparable capacity, frequency, and device size to DRAM. However, the academic research on STT-MRAM main memory remains limited, mainly due to the lack of publicly available detailed timing and current parameters. This study presents a method for cycle accurate simulation of STT-MRAM main memory and releases detailed timing and current parameters, enabling researchers to conduct reliable system-level simulation of STT-MRAM.
ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS
(2022)
Article
Engineering, Electrical & Electronic
Jyotirmoy Chatterjee, Paulo Coelho, Antoine Chavent, Ricardo C. Sousa, Stephane Auffret, Claire Baraduc, Ioan-Lucian Prejbeanu, Bernard Dieny
Summary: In this study, a novel class of hard and out-of-plane magnetized seedless multilayers consisting of [Co/insertion layer/Pt](n) was investigated for potential applications as top reference layers in magnetic tunnel junctions (MTJ). Among various nonferrous insertion layers tested, Ta was found to exhibit the highest perpendicular magnetic anisotropy. By using Ta-inserted SL-MLs, a back-end-of-line (BEOL) compatible top reference layer with more than double the effective perpendicular anisotropy of a conventional top reference layer was achieved. Three types of spintronic memory stacks were developed using this top reference layer, each with unique features and capabilities, such as the ability to withstand high-temperature annealing, faster readout and low-voltage writing, and combining different writing techniques for increased efficiency.
ACS APPLIED ELECTRONIC MATERIALS
(2021)
Article
Engineering, Electrical & Electronic
Chenji Liu, Lan Chen, Xiaoran Hao, Mao Ni
Summary: This article investigates the use of STT-MRAM to reduce main memory energy consumption in IoT terminals and proposes an optimized migration algorithm and experiment scheme to mitigate the adverse effects of poor write performance. The results demonstrate significant reduction in both storage overhead and energy consumption.
IEICE ELECTRONICS EXPRESS
(2022)
Article
Engineering, Electrical & Electronic
Chenji Liu, Lan Chen, Xiaoran Hao, Mao Ni
Summary: The article investigates a hybrid DRAM/STT-MRAM main memory and fast data migration solution to reduce storage overhead, optimize migration algorithm, and consider the impact of system standby time on main memory energy consumption. The study shows significant reduction in storage overhead and energy consumption, especially with longer system standby time.
IEICE ELECTRONICS EXPRESS
(2021)
Article
Computer Science, Hardware & Architecture
Nooshin Mahdavi, Farhad Razaghian, Hamed Farbeh
Summary: This paper proposes a low-cost microarchitectural technique to mitigate write failure and read disturbance in Spin-Transfer Torque Magnetic Random-Accesses Memory (STT-MRAM). By prewriting the blocks and using effective encoding, the reliability of STT-MRAM is improved.
JOURNAL OF SUPERCOMPUTING
(2022)
Article
Engineering, Electrical & Electronic
Zitong Zhang, Wenjie Wang, Pingping Yu, Yanfeng Jiang
Summary: The paper focuses on simulating the scaling roadmap of STT-MRAM using Destiny and explores its performance evaluation in cache applications. It shows that STT-MRAM can achieve performance optimization under certain conditions, with large-capacity memory banks performing better and LOP device model effectively reducing energy consumption.
INTERNATIONAL JOURNAL OF ELECTRONICS
(2022)
Article
Engineering, Electrical & Electronic
Ramit Dutta, Shafin Bin Hamid, Jia Hao Lim, Joel Tan, Bejoy Sikder, Nagarajan Raghavan, Kin Leong Pey, Md Zunaid Baten
Summary: The impact of intracell magnetic coupling on the device-to-device variability of STT-MRAMs is investigated through experiments and simulations. It is found that the measured switching voltages of CoFeB/MgO STT-MRAMs are correlated with the offset fields from magnetic measurements. The correlation is traced back to the stray field arising from intracell magnetic coupling.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Bi Wu, Kai Liu, Tianyang Yu, Haonan Zhu, Ke Chen, Chenggang Yan, Erya Deng, Weiqiang Liu
Summary: With the development of AI and BNN, the traditional computing system faces challenges in terms of memory and power. To improve computing efficiency, a CiM architecture is proposed, using STT-MRAM as the carrier. By optimizing the reading characteristics of STT-MRAM and modifying the peripheral circuitry, higher performance and lower energy consumption can be achieved.
IEEE TRANSACTIONS ON NANOTECHNOLOGY
(2023)
Article
Computer Science, Information Systems
Van-Tinh Nguyen, Quang-Kien Trinh, Renyuan Zhang, Yasuhiko Nakashima
Summary: This paper introduces an in-memory BSNN based on STT-MRAM, utilising surrogate gradient learning to shorten time steps while maintaining accuracy. At the circuit level, presynaptic spikes are input into memory units via differential bit lines, with binarized weights stored in nonvolatile STT-MRAM, enabling high parallelism.
Article
Computer Science, Hardware & Architecture
Nooshin Mahdavi, Farhad Razaghian, Hamed Farbeh
Summary: This study improves the reliability of computer system main memory with minimal changes in architecture, reducing the probability of write and retention failures.
MICROPROCESSORS AND MICROSYSTEMS
(2022)
