Journal
JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS
Volume 19, Issue -, Pages S208-S214Publisher
SPRINGER
DOI: 10.1007/s10854-008-9648-7
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Funding
- Engineering and Physical Sciences Research Council [EP/E031625/1, TS/G001383/1, EP/E035167/1] Funding Source: researchfish
- EPSRC [TS/G001383/1, EP/E031625/1, EP/E035167/1] Funding Source: UKRI
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Two methods for GaN growth on sapphire by metal-organic vapour phase epitaxy are discussed. The first involves only two-dimensional (2D) growth, and results in a high dislocation density, but also a high electrical resistivity. The second involves initial growth of three-dimensional (3D) islands employing a low V:III ratio, followed by island coalescence at a high V: III ratio. It is often assumed that threading dislocations (TDs) form via the coalescence of 3D islands, but detailed atomic force microscopy studies on partially coalesced samples find no evidence of an increased TD density at coalescence boundaries, suggesting that other possible origins for TDs should be considered. The 3D-2D growth method allows TD densities as low as 1.1 x 10(8) cm(-2) to be achieved, but unlike the 2D growth samples these layers are not highly resistive. Scanning capacitance microscopy is used to demonstrate the presence of an unintentionally doped layer close to the GaN/sapphire interface. To simultaneously achieve a reduced TD density compared to 2D growth samples and a high resistivity, a high temperature AlN buffer layer may be employed.
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