Journal
JAPANESE JOURNAL OF APPLIED PHYSICS
Volume 51, Issue 11, Pages -Publisher
IOP PUBLISHING LTD
DOI: 10.1143/JJAP.51.11PB02
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- Grants-in-Aid for Scientific Research [22760248] Funding Source: KAKEN
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We proposed and computationally analyzed a nonvolatile power-gating field-programmable gate array (NVPG-FPGA) based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits of the NVPG-FPGA. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power gating (PG). The break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET, which allows highly efficient PG operations with fine granularity, were proposed. (C) 2012 The Japan Society of Applied Physics
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