Design of an ultralow power CNTFET based 9T SRAM with shared BL and half select free techniques

A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design

(2016) Woong Choi et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors

(2015) Yanan Sun et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications

(2010) Meng-Fan Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

(2010) Ming-Hsien Tu et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array

(2010) Jaydeep P. Kulkarni et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection

(2009) Sheng Lin et al.   IEEE TRANSACTIONS ON NANOTECHNOLOGY

Nanotube electronics for radiofrequency applications

(2009) Chris Rutherglen et al.   Nature Nanotechnology

Exploring Variability and Performance in a Sub-200-mV Processor

(2008) Scott Hanson et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Characterization of a Novel Nine-Transistor SRAM Cell

(2008) Zhiyu Liu et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS