Article
Telecommunications
Srdan Brkic, Predrag Ivanis, Bane Vasic
Summary: This paper proposes a novel framework for designing decoders for Low-Density Parity Check (LDPC) codes, which outperforms Belief-Propagation (BP) decoding on binary symmetric channels in terms of frame error rate performance. The framework incorporates an adaptation method based on the genetic optimization algorithm into the Gradient Descent Bit-Flipping Decoding with Momentum (GDBF-w/M). Numerical examples using codes from IEEE 802.3an and 5GNR standards verify the superior performance of the proposed decoder compared to state-of-the-art bit-flipping decoders. The framework provides a systematic method for decoder optimization without requiring knowledge of trapping sets, and is applicable to both regular and irregular LDPC codes.
IEEE COMMUNICATIONS LETTERS
(2022)
Article
Engineering, Electrical & Electronic
Bin Dai, Chenyu Gao, Zhiyuan Yan, Rongke Liu
Summary: SC-Flip algorithms aim to improve error performance of polar codes by identifying and flipping erroneous hard decisions to reduce error propagation. Unlike existing algorithms, the new SC-Flip decoders utilize both CRC and distributed parity checks to detect and locate incorrectly decoded bits, while introducing a new metric to assist in locating incorrect hard decisions.
IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY
(2021)
Article
Computer Science, Hardware & Architecture
Lanlan Cui, Xiaojian Liu, Fei Wu, Zhonghai Lu, Changsheng Xie
Summary: This article introduces a low-density parity-check (LDPC) decoding algorithm for NAND flash memory, focusing on the tradeoff between implementation complexity and decoding performance. The proposed low-bit-width decoding scheme, using quasi-cyclic LDPC (QC-LDPC) and improved row-layered normalized min-sum algorithm, achieves a lower uncorrectable bit error rate (UBER) without significantly increasing computational complexity.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2022)
Article
Telecommunications
Weigang Chen, Ting Wang, Changcai Han, Jinsheng Yang
Summary: The study introduces the use of high-rate Reed-Solomon (RS) codes as outer codes to construct LDPC-RS product codes, aiming to eliminate the error floor phenomenon of LDPC codes and effectively utilize the erasure-correction capability through a hybrid error-erasure-correction decoding algorithm for the outer code. The overall performance of product codes is enhanced by iteration between outer and inner codes.
CHINA COMMUNICATIONS
(2021)
Article
Computer Science, Information Systems
Anthony Leverrier, Gilles Zemor
Summary: We present sequential and parallel decoders for quantum Tanner codes, which can correct arbitrary errors of weight linear in the code length, respectively in linear or logarithmic time. By applying the Tanner code construction to an expanding square complex with robust local codes, we obtain a family of asymptotically good quantum low-density parity-check codes. Additionally, the same decoders can be easily adapted to the expander lifted product codes of Panteleev and Kalachev. We also provide a tighter bound on the minimum distance of quantum Tanner codes by exploiting recently established bounds on the robustness of random tensor codes.
IEEE TRANSACTIONS ON INFORMATION THEORY
(2023)
Article
Engineering, Electrical & Electronic
Diego Lentner, Emna Ben Yacoub, Stefano Calabro, Georg Bocherer, Nebojsa Stojanovic, Gerhard Kramer
Summary: This article studies concatenated forward error correction using an outer KP4 Reed-Solomon code with hard-decision decoding and inner single parity check (SPC) codes with Chase/Wagner soft-decision decoding. Analytical expressions are derived for the end-to-end frame and bit error rates for transmission over additive white Gaussian noise channels with binary phase-shift keying (BPSK) and quaternary amplitude shift keying (4-ASK), as well as with symbol interleavers and quantized channel outputs. The BPSK error rates are compared to those of two other inner codes: a two-dimensional product code with SPC component codes and an extended Hamming code. Simulation results for unit-memory inter-symbol interference channels and 4-ASK are also presented. The results show that the coding schemes achieve similar error rates, but SPC codes have the lowest complexity and permit flexible rate adaptation.
JOURNAL OF LIGHTWAVE TECHNOLOGY
(2023)
Article
Physics, Multidisciplinary
Predrag Ivanis, Srdjan Brkic, Bane Vasic
Summary: A novel variant of the gradient descent bit-flipping (GDBF) algorithm is proposed for decoding low-density parity-check (LDPC) codes. The algorithm utilizes reliability information from neighboring nodes to determine the bit-flipping rule and extracts and flips suspicious bits based on the satisfaction of checks connecting suspicious nodes. The algorithm is deterministic, resulting in low complexity, and outperforms state-of-the-art hard-decision decoding algorithms.
Article
Engineering, Electrical & Electronic
Mingyang Zhu, Ming Jiang, Chunming Zhao, Fan Yu
Summary: This paper presents a product coding scheme based on binary images of Reed-Solomon (RS) codes and single-parity-check (SPC) codes for high-speed communications. The proposed hybrid soft- and hard-decision iterative decoding algorithms for these codes ensure low hardware and computational complexities by terminating RS component decoders early. The hybrid ID of RS-SPC product codes performs comparable to soft-decision decoding of LDPC codes and BTCs, with lower computational complexity and smaller decoder data flow.
IEEE TRANSACTIONS ON COMMUNICATIONS
(2023)
Article
Engineering, Electrical & Electronic
Seokju Han, Jieun Oh, Kyungmok Oh, Jeongseok Ha
Summary: The paper proposes a deep-learning based decoding algorithm tailored for breaking trapping sets in LDPC codes. By re-initializing the channel outputs for error variable nodes, the decoding failures are resolved, significantly improving the performance in the low error-rate regime.
IEEE TRANSACTIONS ON COMMUNICATIONS
(2022)
Article
Telecommunications
Yihuan Liao, Min Qiu, Jinhong Yuan
Summary: In this work, a novel windowed decoding algorithm for DBICM is proposed to improve the detection on all sub-blocks using extrinsic information, outperforming the original decoding based on numerical results.
IEEE COMMUNICATIONS LETTERS
(2021)
Article
Engineering, Electrical & Electronic
Irina E. Bocharova, Boris D. Kudryashov, Evgenii P. Ovsyannikov, Vitaly Skachek, Tahvend Uustalu
Summary: This article proposes a novel approach to optimizing nonbinary quasi-cyclic LDPC codes by constructing check matrices and labeling field elements. It analyzes the performance of the codes and compares them with other related LDPC codes. The results show that this method accurately predicts the decoding performance of LDPC codes in practical applications.
IEEE TRANSACTIONS ON COMMUNICATIONS
(2022)
Article
Telecommunications
Yang Liu, Huiqin Du, Shancheng Zhao, Jinming Wen
Summary: This letter aims to improve the performance of LDPC coded spatial modulation by introducing delayed bit-interleaved coded spatial modulation (DBICSM). The LDPC-DBICSM encoding structure is presented, along with a non-iterative decoder that works on two blocks of received sequences for LDPC-BICSM. An estimated lower bound on the performance of LDPC-DBICSM is also provided. Extensive simulation results demonstrate the performance advantages of LDPC-DBICSM compared to LDPC-BICSM, with a performance gain of about 1.25 dB achieved at a BER of 10-8.
IEEE COMMUNICATIONS LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Li Deng, Zilong Liu, Yong Liang Guan, Xiaobei Liu, Chaudhry Adnan Aslam, Xiaoxi Yu, Zhiping Shi
Summary: This article introduces enhancements to traditional adaptive belief propagation (ABP) decoding technique for high-density parity-check (HDPC) algebraic codes, aiming to improve performance by incorporating unstable bits with large LLRs and applying partial layered scheduling or hybrid dynamic scheduling. Simulation results demonstrate that the proposed Perturbed ABP (P-ABP) decoding algorithms lead to improved error correction performances and faster convergence rates compared to prior-art ABP variants.
IEEE TRANSACTIONS ON COMMUNICATIONS
(2021)
Article
Engineering, Electrical & Electronic
Alireza Sheikh, Alexandre Graell i Amat, Alex Alvarado
Summary: The paper introduces two new decoding algorithms for improving the performance of iBDD-CR on PCs and SCCs, utilizing error and erasure decoding of component codes for an additional decoding attempt. These algorithms only require the exchange of hard messages between component decoders, making them suitable for ultra high-throughput fiber-optic systems.
JOURNAL OF LIGHTWAVE TECHNOLOGY
(2021)
Article
Telecommunications
Yangcan Zhou, Yaojie Zheng, Zhongfeng Wang
Summary: This study proposes a fast SC (FSC) decoding method to reduce the latency of polar code decoding by applying parallel decoders to specific nodes in the binary decoding tree. The study also explores multiple special nodes of 5G polar codes, investigates their characteristics, and develops corresponding fast decoders that significantly reduce decoding latency without degrading error-correction performance.
IEEE COMMUNICATIONS LETTERS
(2023)
Article
Chemistry, Analytical
William Maher, Joel Waring, Frank Krikowa, Elliott Duncan, Simon Foster
ENVIRONMENTAL CHEMISTRY
(2018)
Article
Engineering, Electrical & Electronic
Honglan Jiang, Leibo Liu, Pieter P. Jonker, Duncan G. Elliott, Fabrizio Lombardi, Jie Han
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2019)
Article
Radiology, Nuclear Medicine & Medical Imaging
Carlos F. Uribe, Sulantha Mathotaarachchi, Vincent Gaudet, Kenneth C. Smith, Pedro Rosa-Neto, Francois Benard, Sandra E. Black, Katherine Zukotynski
JOURNAL OF NUCLEAR MEDICINE
(2019)
Article
Agronomy
Hayley C. Norman, Elliott G. Duncan, David G. Masters
GRASS AND FORAGE SCIENCE
(2019)
Article
Radiology, Nuclear Medicine & Medical Imaging
Katherine Zukotynski, Vincent Gaudet, Phillip H. Kuo, Sabrina Adamo, Maged Goubran, Christopher Scott, Christian Bocti, Michael Borrie, Howard Chertkow, Richard Frayne, Robin Hsiung, Robert Laforce, Michael D. Noseworthy, Frank S. Prato, Demetrios J. Sahlas, Eric E. Smith, Vesna Sossi, Alexander Thiel, Jean-Paul Soucy, Jean-Claude Tardif, Sandra E. Black
CLINICAL NUCLEAR MEDICINE
(2019)
Article
Engineering, Electrical & Electronic
Khaled Al-Amoodi, Rashid Mirzavand, Mohammad Mahdi Honari, Jordan Melzer, Duncan G. Elliott, Pedram Mousavi
IEEE ANTENNAS AND WIRELESS PROPAGATION LETTERS
(2020)
Article
Computer Science, Information Systems
Rachna Srivastava, Vincent C. Gaudet, Patrick Mitran
Summary: This paper presents an FPGA implementation of a fixed-point LDLC decoder, which approximates Gaussian mixture messages to a single Gaussian for improved performance. A quantization study is conducted to determine the required number of bits, and efficient numerical methods are devised to approximate the non-linear functions. A novel pipelined LDLC decoder architecture is proposed, achieving high throughput by resource re-utilization and pipelining.
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
(2022)
Proceedings Paper
Engineering, Electrical & Electronic
Katherine Zukotynski, Vincent C. Gaudet, Phillip Kuo, Sabrina Adamo, Maged Goubran, Christian Bocti, Michael Borrie, Howard Chertkow, Richard Frayne, Robin Hsiung, Robert Jr. Laforce, Michael D. Noseworthy, Frank S. Prato, Jim D. Sahlas, Christopher Scott, Eric E. Smith, Vesna Sossi, Alex Thiel, Jean-Paul Soucy, Jean-Claude Tardif, Sandra E. Black
2019 IEEE 49TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL)
(2019)
Proceedings Paper
Optics
Timothy R. Harrison, Graham J. Hornig, Jorge Marin, Lintong Bu, Seyed Azmayesh-Fard, Duncan G. Elliott, Raymond G. DeCorby
NEXT-GENERATION SPECTROSCOPIC TECHNOLOGIES XII
(2019)
Proceedings Paper
Engineering, Electrical & Electronic
Khaled Al-Amoodi, Rashid Mirzavand, Mohammad Mahdi Honan, Jordan Melzer, Duncan Elliott, Pedram Mousavi
2018 IEEE ANTENNAS AND PROPAGATION SOCIETY INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION & USNC/URSI NATIONAL RADIO SCIENCE MEETING
(2018)
Article
Chemistry, Analytical
William Maher, Elliott Duncan, Hayden Martin, Peter Snell, Frank Krikowa, Rajani Jagtap, Simon Foster, Tariq Ezaz, Michael J. Ellwood
ENVIRONMENTAL CHEMISTRY
(2018)
Proceedings Paper
Engineering, Electrical & Electronic
Jinghang Liang, Duncan G. Elliott
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
(2018)
Article
Computer Science, Hardware & Architecture
Firat Artuger, Fatih Ozkaynak
Summary: The unpredictable nature of chaotic systems makes chaos theory attractive for cryptology studies. However, the cryptographic properties of chaotic systems based on electronic circuit implementation are not as good as those based on mathematical transformations. The proposed post-processing algorithm can improve the nonlinearity values of chaos-based s-box structures, and may have potential applications in the future.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
Yihong Gong, Qibin Chen, Ruiyong Tu, Sini Wu, Jin Xie, Qiyan Sun, Jinghu Li, Zhicong Luo
Summary: In the design of CMOS optical receivers, it is challenging to balance the bandwidth, noise, and gain of the transimpedance amplifier (TIA). This study proposes a 5-stage cascaded TIA to improve performance without using bandwidth expansion techniques.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
Payal Shah, Satvik Sawant, Reena Sonkusare, Surendra S. Rathod
Summary: This paper proposes an asynchronous receptive circuit for cone cells, which mimics the behavior of different cells in the retinal pathway and achieves a similar biological behavior. The circuit is event-based and can detect wavelengths in the visible spectrum.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
Zhi-Guo Yu, Xiao-Yu Zhong, Xiao-Jie Ma, Xiao-Feng Gu
Summary: This paper proposes a Withering-logic Based Issue Queue (W-IQ) to improve the performance of RISC-V processors by increasing IPC and reducing delay. Experimental results show that W-IQ outperforms traditional methods in terms of running time and delay.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
Viet-Thanh Pham, Andrei Velichko, Van Van Huynh, Antonio Vincenzo Radogna, Giuseppe Grassi, Salah Mahmoud Boulaaras, Shaher Momani
Summary: This paper presents a model of a memristive map that utilizes the nonlinearity of memristors to generate complex behavior. The proposed model allows for adjustments in the number of fixed points and symmetry through modifications to the control component. Experimental results demonstrate the feasibility and potential of the model in chaos-based applications.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
Lalit Bandil, Bal Chand Nagar
Summary: This paper investigates the benefits of approximate computing in energy-efficient error-resilient applications. It proposes a modified restoring array square root (MRAS) architecture for approximate computing and presents a trade-off between accuracy and hardware. The results show significant reductions in power consumption and faster computation compared to exact designs.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
Xuhui Wang, Jun Cheng, Fan Chang, Lei Zhu, Han Chang, Kuizhi Mei
Summary: This study proposes an enhanced VTA architecture, which achieves parallel loading of feature maps and weight data by redesigning and optimizing the VTA memory access microarchitecture, fully utilizing bandwidth resources. The experimental results demonstrate significant performance improvement of the proposed architecture, with higher speedup and power efficiency compared to other full-stack accelerator designs.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
Prakash Kumar Rout, Debiprasad Priyabrata Acharya, Debasish Nayak, Umakanta Nanda
Summary: A novel technique for performance optimization and fabrication process variation tolerance of integrated circuits is proposed in this work. The technique is validated in two example cases and shows promising results.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
Jani Babu Shaik, Siona Menezes Picardo, Sonal Singhal, Nilesh Goel
Summary: This study focuses on the impact of reliability issues on the performance of neuromorphic circuits and proposes novel reliability-aware designs to address these issues.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
Saeed Ullah, Xinge Liu, Adil Waheed, Shuailei Zhang
Summary: This paper proposes a new method, based on a chaotic system, for constructing an initial S-box, as well as a novel key-based permutation technique to construct the final S-box. The results show that the S-boxes obtained using this method are stronger and have demonstrated good performance in secure communication and image encryption applications.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
David Arnaiz, Francesc Moll, Eduard Alarcon, Xavier Vilajosana
Summary: This paper proposes an energy and relevance-aware monitoring method that optimizes the behavior of sensor nodes based on self-awareness principles. By balancing relevance and power consumption, and coordinating two adaptive schemes, this method can achieve the target battery life while improving monitoring accuracy.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
Muhammad Umair Safdar, Tariq Shah, Asif Ali, Tanveer ul Haq
Summary: A substitution box (S-box) is a crucial component in symmetric key encryption, and its performance and security level have a direct impact on the encryption scheme. The conventional approach to generate S-boxes involves using Galois fields. This study presents a novel construction of lookup tables using the non-chain ring structure of cardinality 512, which results in a more complex S-box. The use of non-chain ring encryption enhances security, algorithm complexity, resistance to attacks, and computational performance. The proposed S-box encryption technique is statistically, differentially, and security-wise superior to existing methods, making it more effective for image encryption.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
Maoyuan Qin, Jiacheng Zhu, Baolei Mao, Wei Hu
Summary: This paper presents a hardware/software security co-verification method based on information flow analysis, which effectively detects and locates security vulnerabilities in a system. The information flow security model and properties are described using standard hardware design and verification languages.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
Rezaul Haque, Siraj Fulum Mossa
Summary: This paper discusses the challenges and methods of constructing an on-chip low-power energy harvesting block for 3D Non-volatile memory. The focus is on developing a smaller area, higher-efficiency on-chip charge pump design to keep up with transistor scaling every two years. The study presents design criteria and principles, and recommends optimizing circuit placement and following industry-wide design guidelines.
INTEGRATION-THE VLSI JOURNAL
(2024)
Article
Computer Science, Hardware & Architecture
Shaohui Yan, Bian Zheng, Jianjian Wang, Yu Cui, Lin Li, Jiawei Jiang
Summary: In this paper, a three-dimensional conservative system is proposed and analyzed, showing that it is a non-Hamiltonian system. Different attractors are observed by changing the values of the system parameters, indicating rich coexistence phenomena. The complexity of the system is studied to determine the optimal initial state for synchronization. The system is successfully implemented in analog and digital circuits, proving its feasibility. Finally, the system is applied to backstepping synchronization, paving the way for engineering applications.
INTEGRATION-THE VLSI JOURNAL
(2024)
