4.4 Article

Modular multilevel converter with modified half-bridge submodule and arm filter for dc transmission systems with dc fault blocking capability

Journal

IET POWER ELECTRONICS
Volume 11, Issue 14, Pages 2253-2262

Publisher

INST ENGINEERING TECHNOLOGY-IET
DOI: 10.1049/iet-pel.2018.5081

Keywords

voltage control; power convertors; power transmission control; power transmission faults; HVDC power convertors; bridge circuits; HVDC power transmission; dc fault blocking; short-circuit fault; submodule topology; small-scale MMC prototype; modular multilevel converter; modified half-bridge submodule; suitable converter topology; high-voltage dc transmission systems; dc fault ride performance; substantial improvement; transnational multiterminal dc networks; modified submodule circuit; improved dc fault ride; reduced semiconductor losses; enhanced control flexibility; full-bridge submodules; modularity; semiconductor loss; mixed submodules MMC; half-bridge submodules

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Although a modular multilevel converter (MMC) is universally accepted as a suitable converter topology for the high-voltage dc transmission systems, its dc fault ride performance requires substantial improvement in order to be used in critical infrastructures such as transnational multi-terminal dc (MTDC) networks. Therefore, this study proposes a modified submodule circuit for MMC that offers an improved dc fault ride through the performance with reduced semiconductor losses and enhanced control flexibility compared to that achievable with full-bridge submodules. The use of the proposed submodules allows MMC to retain its modularity; with semiconductor loss similar to that of the mixed submodules MMC, but higher than that of the half-bridge submodules. Besides dc fault blocking, the proposed submodule offers the possibility of controlling ac current in-feed during pole-to-pole dc short-circuit fault, and this makes such submodule increasingly attractive and useful for continued operation of MTDC networks during dc faults. The aforesaid attributes are validated using simulations performed in MATLAB/SIMULINK and substantiated experimentally using the proposed submodule topology on a four-level small-scale MMC prototype.

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