Design and Performance of a Sub-Nano-Ampere Two-Stage Power Management Circuit in 0.35-µm CMOS for Dust-Size Sensor Nodes

Published 2011 View Full Article

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Title
Design and Performance of a Sub-Nano-Ampere Two-Stage Power Management Circuit in 0.35-µm CMOS for Dust-Size Sensor Nodes
Authors
Keywords
-
Journal
IEICE TRANSACTIONS ON ELECTRONICS
Volume E94-C, Issue 7, Pages 1206-1211
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Online
2011-07-01
DOI
10.1587/transele.e94.c.1206

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