Article
Computer Science, Information Systems
Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel
Summary: This paper introduces a security-driven CAD and manufacturing flow for 3D integrated circuits by combining split manufacturing and layout camouflaging techniques, aiming to protect intellectual property and prevent the insertion of hardware Trojans. Extensive security analysis supports the effectiveness and efficiency of entering the third dimension for hardware security.
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
(2021)
Article
Computer Science, Hardware & Architecture
Frank T. Werner, Milos Prvulovic, Alenka Zajic
Summary: This article proposes a new nondestructive method for detecting recycled integrated circuits (ICs) using backscattering side-channel analysis (BSCA). The article explains the impact of aging on the backscattering side-channel signal and validates the findings through simulations. A new detection algorithm based on singular value decomposition is presented, which can distinguish unaged and aged ICs from their backscattered measurements. The proposed method is then validated through experiments, showing its effectiveness in detecting recycled ICs aged for a small fraction of the IC's lifetime (roughly 66 days). The experiments also demonstrate the impact of circuit size and complexity on detection accuracy.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
(2022)
Article
Computer Science, Hardware & Architecture
Virinchi Roy Surabhi, Prashanth Krishnamurthy, Hussam Amrouch, Jorg Henkel, Ramesh Karri, Farshad Khorrami
Summary: This article focuses on the nondestructive golden-free detection of recycled/counterfeit integrated circuits (ICs) by estimating the IC's functional/operational age. Gate-level simulations are used to capture the impact of workload on short-term aging and timing violations. The study demonstrates that short-term aging-induced output bit error patterns can be used to estimate the long-term age of an IC, facilitating the detection of recycled ICs.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2023)
Article
Computer Science, Hardware & Architecture
Huanyu Wang, Henian Li, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi
Summary: Fault-injection attacks pose a significant threat to hardware designs, but the current countermeasures are often costly and lack automation. Therefore, it is crucial to develop an automated framework to identify the most critical security locations in a design and reduce the impact of such attacks.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2022)
Article
Computer Science, Hardware & Architecture
Turki Alnuayri, Saqib Khursheed, Antonio Leonel Hernandez Martinez, Daniele Rossi
Summary: This article focuses on the most counterfeited area-recycled and remarked ICs-and aims to develop a technique to distinguish between new and used digital ICs based on an aging sensor mechanism. The study proposes a novel differential aging sensor to measure the discharge time increase that depends on the subthreshold leakage current due to aging with two on-chip designs. Results show that the discharge time is a sensitive indicator for aging, surpasses frequency in detecting previous usage and is robust against process, voltage, and temperature variations.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
(2021)
Article
Computer Science, Information Systems
Rajit Karmakar, Harshit Kumar, Santanu Chattopadhyay
Summary: Logic encryption is a potential solution to protect Intellectual Property (IP) from piracy and counterfeiting, but recent attacks have raised concerns. A new dynamic obfuscation scheme proposed in this paper aims to protect against SAT attacks by safeguarding the Design-for-Testability (DfT) infrastructure and preventing key leakage through weak gate locations, offering protection against various attacks while maintaining testability. Unlike other SAT preventive schemes, the proposed method does not suffer from output corruption, meeting the fundamental requirements of a logic encryption scheme.
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
(2021)
Article
Computer Science, Theory & Methods
Nimisha Limaye, Satwik Patnaik, Ozgur Sinanoglu
Summary: This research reviews recent provably-secure logic locking (PSLL) techniques and develops a new security diagnostic tool (Valkyrie) for assessing structural vulnerabilities before designing on silicon. A generic circuit-recovery attack is also proposed to validate the tool's effectiveness. The open-source diagnostic tool can test the structural resilience of the hardware implementation of any newly developed PSLL technique.
IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY
(2022)
Article
Computer Science, Information Systems
Hamidur Rahman, A. B. M. Harun-ur Rashid, Mahmudul Hasan
Summary: This paper proposes a new framework for post-synthesis obfuscation of digital circuits using a combination of cells and an Anti-SAT block. The framework integrates obfuscation, Anti-SAT, and benchmark validation using MATLAB, Python, Cadence RTL Encounter, and Cadence LEC. Evaluation metrics including area, delay, leakage power, and total power are adopted. The framework ensures security by reducing the probability of breaking the circuit through the use of multiple types of obfuscated cells and an Anti-SAT block.
Review
Engineering, Manufacturing
Swapnil S. Salvi, Ankur Jain
Summary: Three-dimensional integrated circuits (3-D IC) technology has emerged due to the challenges of dimensional scaling and increasing interconnect delay, offering reduced interconnect delay and enhanced design flexibility. However, vertical integration in a 3-D IC also brings severe thermal management challenges, which require innovative thermal management techniques.
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY
(2021)
Proceedings Paper
Computer Science, Hardware & Architecture
Ashkan Vakil, Farzad Niknia, Ali Mirzaeian, Avesta Sasan, Naghmeh Karimi
Summary: This paper presents a recycled IC detection scheme based on delay side-channel testing, which builds a Neural Network model using features extracted during the design flow and sample delays extracted from the target chip to identify whether the target chip is new or recycled effectively.
2021 26TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)
(2021)
Article
Computer Science, Hardware & Architecture
Yousef Safari, Boris Vaisband
Summary: This article proposes a robust integrated power delivery methodology to address the power delivery challenge in three-dimensional (3-D) integrated circuits (ICs). By exploiting recent advancements in high-density integrated passive components fabrication and the available area in the vertical dimension of 3-D construct, an efficient and robust power delivery system is developed. The proposed methodology exhibits significant improvement in voltage drop and power efficiency compared to three other power delivery topologies.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
(2023)
Article
Engineering, Electrical & Electronic
Hayden Bialek, Matthew L. Johnston, Arun Natarajan
Summary: This article presents a novel architecture for low-power RXs that achieves low power consumption, high sensitivity, and interferer tolerance. The proposed architecture performs well in terms of operating range, sensitivity, and power consumption.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2023)
Article
Computer Science, Hardware & Architecture
Yi-Chen Lu, Sai Pentapati, Lingjun Zhu, Gauthaman Murali, Kambiz Samadi, Sung Kyu Lim
Summary: This article introduces a novel unsupervised graph learning-based tier partitioning framework, TP-GNN, which significantly improves the quality of results in 3D designs, achieving substantial progress in industrial designs and demonstrating broad applicability.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2022)
Article
Computer Science, Theory & Methods
Kaveh Shamsi, Yier Jin
Summary: Many logic locking schemes have been proposed and defeated, particularly by oracle-guided SAT-solver-based attacks. Recent work has begun to define security terms, including exact-functional-secrecy (EFS) and approximate-functional-secrecy (AFS). This paper focuses on EFS and introduces a novel SAT attack called the rare-fast-querying (RFQ) attack, which can automatically deobfuscate high-activity/entropy nets for key-correctness while also discussing techniques to achieve EFS with manageable overhead.
IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY
(2021)
Article
Chemistry, Multidisciplinary
Rekha Panda, Om Shankar Dinkar, Archana Kumari, Rajesh Gupta, Manis Kumar Jha, Devendra Deo Pathak
Summary: The research proposes a new method for recovering precious metals from waste computer PCBs, obtaining a metallic concentrate containing Ag, Au, Pd, and Pt, and successfully treating all generated wastes. Through leaching and precipitation processes, a high recovery rate of Ag, Cu, Pb, and Ni is achieved, while optimizing conditions for efficient use of resources.
JOURNAL OF INDUSTRIAL AND ENGINEERING CHEMISTRY
(2021)