A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder

Title
A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder
Authors
Keywords
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Journal
IEEE TRANSACTIONS ON MULTIMEDIA
Volume 10, Issue 1, Pages 31-42
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2007-12-21
DOI
10.1109/tmm.2007.911299

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