4.6 Article

Nondestructive Measurement of the Residual Stresses in Copper Through-Silicon Vias Using Synchrotron-Based Microbeam X-Ray Diffraction

Journal

IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 61, Issue 7, Pages 2473-2479

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2014.2321736

Keywords

Interconnect; keep-out-zone (KOZ); stress measurement; synchrotron; three-dimensional integrated circuits (3DIC); through-silicon via (TSV); X-ray diffraction

Funding

  1. U.S Department of Energy's (DOE) Office of Science [DE-AC02-06CH11357]

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In this paper, we report a new method for achieving depth resolved determination of the full stress tensor in buried Cu through-silicon vias (TSVs), using a synchrotron-based X-ray microdiffraction technique. Two adjacent Cu TSVs were analyzed; one capped with SiO2 (0.17 mu m) and the other without. The uncapped Cu TSV was found to have higher stresses with an average hydrostatic stress value of 145 +/- 37 MPa, as compared with the capped Cu TSV, which had a value of 89 +/- 28 MPa. Finite element-based parametric analyses of the effect of cap thickness on TSV stress were also performed. The differences in the stresses in the adjacent Cu TSVs were attributed to their microstructural differences and not to the presence of a cap layer. Based on the experimentally determined stresses, the stresses in the surrounding Si for both Cu TSVs were calculated and the FinFET keep-out-zone (KOZ) from the Cu TSV was estimated. The FinFET KOZ is influenced by the microstructural variations in their neighboring Cu TSVs, thus, it should be accounted for in KOZ design rules.

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