Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 60, Issue 4, Pages 1355-1360Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2013.2247763
Keywords
Bosch process; bulk MOSFET; corner effect; deep reactive ion etching (RIE); extension doping; gate-all-around (GAA); junctionless (JL) transistor; short-channel effects (SCEs); vertically stacked silicon nanowire (Si-NW)
Funding
- Center for Integrated Smart Sensors
- Ministry of Education, Science and Technology [CISS-2012M3A6A6054187]
- MKE/KEIT [10035320]
- Samsung Electronics Company, Ltd.
- SK Hynix Semiconductor Inc.
- Korea Evaluation Institute of Industrial Technology (KEIT) [10035320] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
- National Research Foundation of Korea [2011-0031848] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
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A silicon nanowire (Si-NW) with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field-effect transistor (FET). A suspended Si-NW from the bulk-Si is realized using a deep reactive ion etching (RIE) process. The RIE process is iteratively applied to make multiply stacked Si-NWs, which can increase the on-state current when amplified with the number of iterations or enable integration of 3-D stacked Flash memory. The fabricated JL FETs exhibit excellent electrostatic control with the aid of the GAA and junction-free structure. The influence on device characteristics according to the channel dimensions and additional doping at the source and drain extension are studied for various geometric structures of the Si-NW.
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