Under-the-Barrier Model: An Extension of the Top-of-the-Barrier Model to Efficiently and Accurately Simulate Ultrascaled Nanowire Transistors

In this paper, we present a computationally efficient full-band method to determine the current characteristics of circular, gate-all-around nanowire (NW) FETs in the sub-10-nm regime. The well-established top-of-the-barrier model is extended to consider intraband tunneling through the Wentzel-Kramers-Brillouin approximation. The required electrostatic potential is obtained using a parabolic approximation for its radial component, thus reducing Poisson equation to an 1-D problem and the computational burden by several orders of magnitude. After validating the model with 3-D, full-band, atomistic quantum transport simulations, the properties of Si, Ge, and InAs NW FETs are studied as function of their diameter and gate length. It is found that below 10-nm gate lengths Si < 110 > NW transistors outperform Ge < 100 >, independently from their diameter. On the other hand, InAs < 100 > wires with diameters below 6 nm exhibit higher ON-currents than their Si counterparts.