Article
Computer Science, Hardware & Architecture
Jaehun Jang, Jong Hwan Ko
Summary: This paper proposes a method to reduce state errors when storing neural network weights in Flash memory. By applying weight-bit inversion for state elimination and state error reduction, accuracy and read speed can be improved. Furthermore, an adaptive weight-bit inversion scheme is used to selectively operate on units of weight groups, further improving read speed.
JOURNAL OF SYSTEMS ARCHITECTURE
(2022)
Article
Nanoscience & Nanotechnology
Saeyan Choi, Seungsob Kim, Seain Bang, Jungchun Kim, Dong Geun Park, Seunghee Jin, Min Jung Kim, Eunmee Kwon, Jae Woo Lee
Summary: This study investigates the effects of hydrogen post-treatment on 3D NAND flash memory and finds that optimal hydrogen PTA conditions can significantly improve device performance.
Article
Multidisciplinary Sciences
Sangyong Park, Dongyoung Lee, Juncheol Kang, Hojin Choi, Jin-Hong Park
Summary: In this study, a stacked ferroelectric memory array based on laterally gated ferroelectric field-effect transistors (LG-FeFETs) is presented, which exhibits wide memory window, effective ferroelectric switching, long retention time, and high endurance. The feasibility of a 3D stacked structure using LG-FeFETs is verified by performing multiply-accumulate (MAC) operations in a two-tier stacked memory configuration.
NATURE COMMUNICATIONS
(2023)
Article
Mathematics
Hristo Kostadinov, Nikolai Manev
Summary: Memory devices based on floating-gate transistors have become the dominant technology for non-volatile storage devices. Errors observed in flash memory devices are typically of a special, asymmetric type, and integer codes have been shown to be effective in correcting them. This paper presents a new construction of integer codes capable of correcting single errors typical for flash memory devices.
Article
Multidisciplinary Sciences
Yejin Yang, Juhee Jeon, Jaemin Son, Kyoungah Cho, Sangsig Kim
Summary: This study presents a NAND and NOR logic-in-memory (LIM) composed of silicon nanowire feedback field-effect transistors, which can perform both data processing and memory operations. It has the potential to address power and processing speed issues.
SCIENTIFIC REPORTS
(2022)
Review
Chemistry, Analytical
Alessandro S. Spinelli, Gerardo Malavena, Andrea L. Lacaita, Christian Monzio Compagnoni
Summary: This paper reviews the phenomenology of random telegraph noise (RTN) in 3D NAND Flash arrays, discussing the impact of polycrystalline silicon channels and the transition from planar to 3D architectures on RTN dependences. Experimental data are presented and explained through theoretical and simulation models, highlighting the role of highly-defective grain boundaries and localized nature of RTN traps in percolative current transport.
Article
Computer Science, Information Systems
Jun Ho An, Jin Young Chun, Hyun Kook Park, Seong-Ook Jung
Summary: In this paper, a high-speed BL pre-charge scheme and a sense-out-node amplification (SOA) scheme are proposed to improve the read speed and reduce read errors of NAND flash memory. The proposed schemes increase the speed of the BL pre-charge operation by 75% and reduce the read error by 57% in simulations.
Article
Computer Science, Hardware & Architecture
Xiaoliu Feng, Xianzhang Chen, Ruolan Li, Jiali Li, Chunlin Song, Duo Liu, Yujuan Tan, Lei Qiao
Summary: This study proposes a revenue model based cross-layer cooperative discarding mechanism, called CoDiscard, to optimize I/O performance and reduce write amplification. By selecting high performance-price-ratio TRIM commands and using a cross-layer cooperative scheme, write amplification can be significantly reduced and performance improved.
JOURNAL OF SYSTEMS ARCHITECTURE
(2022)
Article
Computer Science, Hardware & Architecture
Myeonggu Kang, Hyeonuk Kim, Hyein Shin, Jaehyeong Sim, Kyeonghan Kim, Lee-Sup Kim
Summary: This article proposes a NAND flash-based DNN accelerator to improve energy efficiency by reducing the burden of the domain conversion process. The accelerator successfully utilizes the bit-level sparsity of DNN, resulting in significant improvements in energy efficiency and throughput.
IEEE TRANSACTIONS ON COMPUTERS
(2022)
Article
Engineering, Electrical & Electronic
Seungmin Lee, Joonsung Lim, Jun Hyoung Kim, Sunghwan Cho, Yong Kyu Lee, Byoungdeog Choi
Summary: This study proposes a novel cell array structure suitable for hybrid bonding technology in 3-D NAND architecture, allowing for the removal of dummy cell area and increase in bit density. The proposed method for programming this structure utilizes the asymmetric GIDL phenomenon for string selection and inhibition, potentially improving V-PASS disturbance.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Computer Science, Hardware & Architecture
Moonseok Jang, Kexin Wang, Sangjin Lee, Hyeonggyu Jeong, Inyeong Song, Yong Ho Song, Jungwook Choi
Summary: This paper proposes a stealth program operation that supports early write completion to hide the program time of flash memory, resulting in a reduction of average write latency in solid-state drives by up to 95.88%.
JOURNAL OF SYSTEMS ARCHITECTURE
(2022)
Article
Computer Science, Information Systems
Junnosuke Kondo, Toru Tanzawa
Summary: This paper investigates the effectiveness of pre-emphasis (PE) pulses to reduce bit-line access time in NAND flash memory, showing significant reductions in sense current delay and BL voltage delay time for both SLM and TLM. Address-dependent PE pulse control can markedly reduce sense current delay, especially for cells closely located to the sensing circuit.
Article
Engineering, Electrical & Electronic
Yuhan Luo, Mingwei Lin, Yubiao Pan, Zeshui Xu
Summary: This paper proposes a novel dual locality-based FTL (DL-FTL) for NAND flash memory, which effectively utilizes the temporal and spatial locality of workloads to improve cache hit ratio and reduce system response time.
IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
(2022)
Article
Engineering, Electrical & Electronic
Sadman Sakib, Aleksandar Milenkovic, Biswajit Ray
Summary: Counterfeit electronics in the global supply chain pose a growing problem, impacting both manufacturers and consumers. The new Flash-DNA technique introduces a unique identifier for NAND flash memory chips, helping prevent the proliferation of rebranded or cloned chips. Experimental evaluation demonstrates that Flash-DNA captures fundamental manufacturing properties, allowing for tracing the origins of NAND flash memory chips.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Computer Science, Information Systems
Jong-Hyeok Park, Dong-Joo Park, Tae-Sun Chung, Sang-Won Lee
Summary: The study proposed a novel crash recovery scheme FastCheck for a hybrid mapping FTL called FAST, which efficiently secures address-mapping information and provides low logging overhead and fast recovery time.
