Journal
IEEE TRANSACTIONS ON COMPUTERS
Volume 62, Issue 4, Pages 631-643Publisher
IEEE COMPUTER SOC
DOI: 10.1109/TC.2011.256
Keywords
Image denoising; impulse noise; impulse detector; architecture
Funding
- National Science Council, R.O.C. [NSC-101-2221-E-006-151-MY3]
- Ministry of Economic Affairs (MOEA) of Taiwan [MOEA 100-EC-17-A-05-S1-192]
- Headquarters of University Advancement at the National Cheng Kung University
- Ministry of Education, Taiwan, R.O.C.
Ask authors/readers for more resources
Images are often corrupted by impulse noise in the procedures of image acquisition and transmission. In this paper, we propose an efficient denoising scheme and its VLSI architecture for the removal of random-valued impulse noise. To achieve the goal of low cost, a low-complexity VLSI architecture is proposed. We employ a decision-tree-based impulse noise detector to detect the noisy pixels, and an edge-preserving filter to reconstruct the intensity values of noisy pixels. Furthermore, an adaptive technology is used to enhance the effects of removal of impulse noise. Our extensive experimental results demonstrate that the proposed technique can obtain better performances in terms of both quantitative evaluation and visual quality than the previous lower complexity methods. Moreover, the performance can be comparable to the higher complexity methods. The VLSI architecture of our design yields a processing rate of about 200 MHz by using TSMC 0.18 mu m technology. Compared with the state-of-the-art techniques, this work can reduce memory storage by more than 99 percent. The design requires only low computational complexity and two line memory buffers. Its hardware cost is low and suitable to be applied to many real-time applications.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available