4.5 Article

RePlAce: Advancing Solution Quality and Routability Validation in Global Placement

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCAD.2018.2859220

Keywords

Global placement; Layout design automation; Numerical analysis; Routability-driven placement

Funding

  1. Qualcomm
  2. Samsung
  3. NXP
  4. NSF [CCF-1564302]

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The Nesterov's method approach to analytic placement has recently demonstrated strong solution quality and scalabifity. We dissect the previous implementation strategy and show that solution quality can be significantly improved using two levers: 1) constraint-oriented local smoothing and 2) dynamic step size adaptation. We propose a new density function that comprehends local overflow of area resources; this enables a constraint-oriented local smoothing at per-bin granularity. Our improved dynamic step size adaptation automatically determines step size and effectively allocates optimization effort to significantly improve solution quality without undue runtime impact. Our resulting global placement tool, RePlAce, achieves an average of 2.00% half-perimeter wire length (HPWL) reduction over all best known ISPD-2005 and ISPD-2006 benchmark results, and an average of 2.73% over all best known modern mixed size (MMS) benchmark results, without any benchmark-specific code or tuning. We further extend our global placer to address mutability, and achieve on average 8.50%-9.59% scaled HPWI, reduction over previous leading academic placers for the DAC-2012 and ICCAD-2012 benchmark suites. To our knowledge, RePlAce is the first work to achieve superior solution quality across all the ISPD-2005, ISPD-2006, MMS, DAC-2012, and ICCAD-2012 benchmark suites with a single global placement engine.

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