4.7 Article

A 100-Channel 1-mW Implantable Neural Recording IC

Journal

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2013.2249175

Keywords

Biomedical application; capacitor-less LDO; current reuse; dual S/H; high power efficiency; low-noise neural amplifier; multi-channel neural recording system; NEF; power and area trade-off; SAR ADC

Funding

  1. Science and Engineering Research Council of A*STAR (Agency for Science, Technology and Research), Singapore, under SERC [1021710162]

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This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 mu V-rms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-mu m standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution formulti-channel neural recording systems.

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