The Design of Fast-Settling Three-Stage Amplifiers Using the Open-Loop Damping Factor as a Design Parameter

This paper presents an open-loop design method for fast-settling three-stage class-A amplifiers. Specifically, using the open-loop damping factor as a design parameter, the presented method delivers robust settling performance of a third-order system in the presence of process and component variation. As an illustration of the proposed approach, we show Spice simulation results of a nested-Miller-compensated three-stage-amplifier designed in 0.35-mu m CMOS technology. The design achieves a 1% and 0.1% dynamic-error settling times of 6.4 ns and 13.7 ns, respectively, at a gain-bandwidth product of 55 MHz and a dynamic range of 80 dB, while consuming 5.4 mW from a 3-V supply.