Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 57, Issue 9, Pages 2542-2551Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2010.2046226
Keywords
Discrete-time triply selective fading channels; field-programmable gate array (FPGA) hardware implementation; multiple-input-multiple-output (MIMO) systems; sum-of-sinusoid (SoS) method; wireless fading channel modeling
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Funding
- Office of Naval Research [N00014-07-1-0219]
- National Science Foundation [ECCS-0846486]
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Hardware implementation of discrete-time triply selective Rayleigh fading channel emulators is proposed for multiple-input-multiple-output (MIMO) communications. The proposed work differs from existing ones in that it incorporates temporal correlation, intertap correlation, and spatial correlation matrices into multiple uncorrelated frequency-flat fading waveforms to obtain a triply selective fading channel. The flat fading waveforms with temporal correlation or Doppler spectrum are generated using a sum-of-sinusoid method. The intertap correlation matrix associated with multipath delay spread is computed according to the channel power delay profile and transmit/receive filters. The spatial correlation matrices are predefined inputs associated with transmit and receive antenna arrangements. The square roots of the three correlation matrices are computed via singular-value decomposition and then combined in real time with the flat fading waveforms. Several fading channel examples are implemented on an Altera Stratix III EP3SL150F field-programmable gate array (FPGA) DSP development kit with fixed-point arithmetics. A 4-by-4 MIMO triply selective channel with ten correlated delay taps per subchannel utilizes one-third of the hardware resource of the FPGA chip. The statistical properties of the emulated fading waveforms match those of the software-based simulators and the theoretical ones. The proposed method achieves good balance between computational complexity and resource utilization.
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